Patents by Inventor Chi-Chou Lin

Chi-Chou Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240113187
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a substrate having one or more interior surfaces forming a recess within an upper surface of the substrate. Source/drain regions are disposed within the substrate on opposing sides of the recess. A first gate dielectric is arranged along the one or more interior surfaces forming the recess, and a second gate dielectric is arranged on the first gate dielectric and within the recess. A gate electrode is disposed on the second gate dielectric. The second gate dielectric includes one or more protrusions that extend outward from a recessed upper surface of the second gate dielectric and that are arranged along opposing sides of the second gate dielectric.
    Type: Application
    Filed: January 5, 2023
    Publication date: April 4, 2024
    Inventors: Jhu-Min Song, Ying-Chou Chen, Yi-Kai Ciou, Chien-Chih Chou, Fei-Yun Chen, Yu-Chang Jong, Chi-Te Lin
  • Patent number: 11830725
    Abstract: Embodiments of the present disclosure generally relate to methods of cleaning a structure and methods of depositing a capping layer in a structure. The method of cleaning a structure includes suppling a cleaning gas, including a first gas including nitrogen (N) and a second gas including fluorine (F), to a bottom surface of a structure. The cleaning gas removes unwanted metal oxide and etch residue from the bottom surface of the structure. The method of depositing a capping layer includes depositing the capping layer over the bottom surface of the structure. The methods described herein reduce the amount of unwanted metal oxides and residue, which improves adhesion of deposited capping layers.
    Type: Grant
    Filed: January 20, 2021
    Date of Patent: November 28, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Naomi Yoshida, He Ren, Hao Jiang, Chenfei Shen, Chi-Chou Lin, Hao Chen, Xuesong Lu, Mehul B. Naik
  • Publication number: 20230377879
    Abstract: Embodiments of the present disclosure are related to methods of preventing aluminum diffusion in a metal gate stack (e.g., high-? metal gate (HKMG) stacks and nMOS FET metal gate stacks). Some embodiments relate to a barrier layer for preventing aluminum diffusion into high-? metal oxide layers. The barrier layer described herein is configured to reduce threshold voltage (Vt) shift and reduce leakage in the metal gate stacks. Additional embodiments relate to methods of forming a metal gate stack having the barrier layer described herein. The barrier layer may include one or more of amorphous silicon (a-Si), titanium silicon nitride (TiSiN), tantalum nitride (TaN), or titanium tantalum nitride (TiTaN).
    Type: Application
    Filed: May 18, 2022
    Publication date: November 23, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Srinivas Gandikota, Elizabeth Mao, Tianyi Huang, Tengzhou Ma, Chi-Chou Lin, Yixiong Yang
  • Publication number: 20230313378
    Abstract: Substrate support, substrate support assemblies and process chambers comprising same are described. The substrate support has a thermally conductive body with a top surface, a bottom surface and an outer edge, and a plurality of long edge purge channel outlet opening at the outer edge of the thermally conductive body. The substrate support is configured to support a substrate to be processed on a top surface of the substrate support. The top surface of the thermally conductive body may have a ceramic coating. Each of the plurality of purge channel outlet is in fluid communication with a long edge purge channel. The long edge purge channel is coated with a long edge purge channel coating. A substrate support assembly includes the substrate support and the support post coupled to the substrate support. The processing chamber include a chamber body and the substrate support within the chamber body.
    Type: Application
    Filed: March 31, 2022
    Publication date: October 5, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Yongjing Lin, Lei Zhou, Muhannad Mustafa, Shih Chung Chen, Zhihui Liu, Chi-Chou Lin, Bin Cao, Janardhan Devrajan, Mario D. Silvetti, Mandyam Sriram
  • Patent number: 11659288
    Abstract: An image sensing device that can adjust parameters of an image before sending it to a processor for reducing computing power and/or storage requirement is disclosed. The image sensing device includes an array of sensing pixels; an output amplifier; an analog-to-digital converter; a first set of registers and a second set of registers; an activation circuit; and a profiling logic. The profiling logic conducts statistical analysis on output data and adjusts parameters stored in the first set of registers until results of the statistical analysis reaches a target standard, wherein the adjusted parameters are used to generate an output image by each sensing pixel of the array of sensing pixels once the target standard is reached and a notification signal is sent to an external device for notifying the failure of parameter adjustment if the target standard fails to be reached within a predetermined times of adjustment.
    Type: Grant
    Filed: October 22, 2020
    Date of Patent: May 23, 2023
    Assignee: SunASIC Technologies, Inc.
    Inventors: Chi-Chou Lin, Zheng-Ping He
  • Publication number: 20230113514
    Abstract: Processing methods described herein comprise forming a metal gate film on a narrow feature and a wide feature and depositing a hard mask on the metal gate film. The hard mask forms on the metal gate film at a top, bottom and sidewalls of the wide feature and on a top of the narrow feature to cover the metal gate film. Some processing methods comprise oxidizing the metal gate film on the narrow feature to convert a portion of the metal gate film to a metal oxide film. Some processing methods comprise etching the metal oxide film from the narrow feature to leave a gradient etch profile. Some processing methods comprise filling the narrow feature and the wide feature with a gap fill material comprising one or more of a metal nitride, titanium nitride (TiN) or titanium oxynitride (TiON), the gap fill material substantially free of seams and voids.
    Type: Application
    Filed: December 3, 2021
    Publication date: April 13, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Shih Chung Chen, Yongjing Lin, Chi-Chou Lin, Zhiyong Wang, Chih-Hsun Hsu, Mandyam Sriram, Tza-Jing Gung
  • Patent number: 11355391
    Abstract: The present disclosure generally relates to methods for processing of substrates, and more particularly relates to methods for forming a metal gapfill. In one implementation, the method includes forming a metal gapfill in an opening using a multi-step process. The multi-step process includes forming a first portion of the metal gapfill, performing a sputter process to form one or more layers on one or more side walls, and growing a second portion of the metal gapfill to fill the opening with the metal gapfill. The metal gapfill formed by the multi-step process is seamless, and the one or more layers formed on the one or more side walls seal any gaps or defects between the metal gapfill and the side walls. As a result, fluids utilized in subsequent processes do not diffuse through the metal gapfill.
    Type: Grant
    Filed: February 27, 2020
    Date of Patent: June 7, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Xi Cen, Feiyue Ma, Kai Wu, Yu Lei, Kazuya Daito, Yi Xu, Vikash Banthia, Mei Chang, He Ren, Raymond Hoiman Hung, Yakuan Yao, Avgerinos V. Gelatos, David T. Or, Jing Zhou, Guoqiang Jian, Chi-Chou Lin, Yiming Lai, Jia Ye, Jenn-Yue Wang
  • Publication number: 20220132053
    Abstract: An image sensing device that can adjust parameters of an image before sending it to a processor for reducing computing power and/or storage requirement is disclosed. The image sensing device includes an array of sensing pixels; an output amplifier; an analog-to-digital converter; a first set of registers and a second set of registers; an activation circuit; and a profiling logic. The profiling logic conducts statistical analysis on output data and adjusts parameters stored in the first set of registers until results of the statistical analysis reaches a target standard, wherein the adjusted parameters are used to generate an output image by each sensing pixel of the array of sensing pixels once the target standard is reached and a notification signal is sent to an external device for notifying the failure of parameter adjustment if the target standard fails to be reached within a predetermined times of adjustment.
    Type: Application
    Filed: October 22, 2020
    Publication date: April 28, 2022
    Inventors: Chi-Chou Lin, Zheng-Ping He
  • Publication number: 20220098731
    Abstract: Methods of forming electronic devices comprising tungsten film stacks are provided. Methods include forming a tungsten nucleation layer on the barrier layer using an atomic layer deposition (ALD) process including a tungsten precursor that is free of fluorine. Forming the nucleation layer comprises controlling process parameters and/or forming WSi pre-nucleation layer.
    Type: Application
    Filed: September 29, 2020
    Publication date: March 31, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Kedi Wu, Chenfei Shen, Chi-Chou Lin, Ilanit Fisher, Shih Chung Chen, Mandyam Sriram, Srinivas Gandikota
  • Publication number: 20220064785
    Abstract: Embodiments of the present disclosure generally relate chamber lids and methods of using such for gas-phase particle reduction. In an embodiment is provided a chamber lid that includes a top wall, a bottom wall, a plurality of vertical sidewalls, and an interior volume within the chamber lid defined by the top wall, the bottom wall, and the plurality of vertical sidewalls. The chamber lid further includes a plurality of air flow apertures, wherein the plurality of air flow apertures is configured to fluidly communicate air into the interior volume and out of the interior volume, and a mesh disposed on a face of at least one of the air flow apertures of the plurality of air flow apertures. In another embodiment is provided a method of processing a substrate in a substrate processing chamber, the substrate processing chamber comprising a chamber lid as described herein.
    Type: Application
    Filed: September 2, 2020
    Publication date: March 3, 2022
    Inventors: Muhannad MUSTAFA, Haoyan SHA, Muhammad M. RASHEED, Chi-Chou LIN, Mario D. SILVETTI, Bin CAO, Shihchung CHEN, Yongjing LIN
  • Publication number: 20210384035
    Abstract: Methods of forming metallic tungsten films selectively on a conductive surface relative to a dielectric surface are described. A substrate is exposed to a first process condition to deposit a fluorine-free metallic tungsten film. The fluorine-free metallic tungsten film is exposed to a second process condition to deposit a tungsten film on the fluorine-free metallic tungsten film.
    Type: Application
    Filed: April 8, 2021
    Publication date: December 9, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Ilanit Fisher, Shih Chung Chen, Kedi Wu, Ashley Lin, Chi-Chou Lin, Yi Xu, Yu Lei, Mandyam Sriram, Wen Ting Chen, Srinivas Gandikota, Chenfei Shen, Naomi Yoshida, He Ren
  • Publication number: 20210384036
    Abstract: Methods of forming metallic tungsten films selectively on a conductive surface relative to a dielectric surface are described. A substrate is exposed to a first process condition to deposit a tungsten-containing film that is substrate free of tungsten metal. The tungsten-containing film is then converted to a metallic tungsten film by exposure to a second process condition.
    Type: Application
    Filed: June 4, 2021
    Publication date: December 9, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Ilanit Fisher, Chi-Chou Lin, Kedi Wu, Wen Ting Chen, Shih Chung Chen, Srinivas Gandikota, Mandyam Sriram, Chenfei Shen, Naomi Yoshida, He Ren
  • Patent number: 11187721
    Abstract: An electronic device having a structure that electrically connects the contactor to an electronic device during a testing process is disclosed. The contactor includes a holder for accommodating the electronic device during the testing process; a flexible circuit, having a first set of contacts electrically connected to the corresponding electrode terminals of the electronic device, and a second set of contacts electrically connected to a control unit that sends test signals during the test process; an elastomer, for adjusting the pressure between the first set of contacts of the flexible circuit and the corresponding electrode terminals of the electronic device while being pressed together; and an alignment tool, for aligning the first set of contacts with the corresponding electrode terminals of the electronic device. The electrode terminals of the electronic device are located on the same surface of the electronic device and the flexible circuit is detachable from the contactor.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: November 30, 2021
    Assignee: SunASIC Technologies, Inc.
    Inventors: Chi-Chou Lin, Hsien-Hsueh Lee, Zheng-Ping He
  • Publication number: 20210239733
    Abstract: An electronic device having a structure that electrically connects the contactor to an electronic device during a testing process is disclosed. The contactor includes a holder for accommodating the electronic device during the testing process; a flexible circuit, having a first set of contacts electrically connected to the corresponding electrode terminals of the electronic device, and a second set of contacts electrically connected to a control unit that sends test signals during the test process; an elastomer, for adjusting the pressure between the first set of contacts of the flexible circuit and the corresponding electrode terminals of the electronic device while being pressed together; and an alignment tool, for aligning the first set of contacts with the corresponding electrode terminals of the electronic device. The electrode terminals of the electronic device are located on the same surface of the electronic device and the flexible circuit is detachable from the contactor.
    Type: Application
    Filed: February 3, 2020
    Publication date: August 5, 2021
    Inventors: Chi-Chou LIN, Hsien-Hsueh LEE, Zheng-Ping HE
  • Publication number: 20210233765
    Abstract: Embodiments of the present disclosure generally relate to methods of cleaning a structure and methods of depositing a capping layer in a structure. The method of cleaning a structure includes suppling a cleaning gas, including a first gas including nitrogen (N) and a second gas including fluorine (F), to a bottom surface of a structure. The cleaning gas removes unwanted metal oxide and etch residue from the bottom surface of the structure. The method of depositing a capping layer includes depositing the capping layer over the bottom surface of the structure. The methods described herein reduce the amount of unwanted metal oxides and residue, which improves adhesion of deposited capping layers.
    Type: Application
    Filed: January 20, 2021
    Publication date: July 29, 2021
    Inventors: Naomi YOSHIDA, He REN, Hao JIANG, Chenfei SHEN, Chi-Chou LIN, Hao CHEN, Xuesong LU, Mehul B. NAIK
  • Patent number: 11018009
    Abstract: The present disclosure relates to a method for forming a p-metal work function nitride film having a desired p-work function on a substrate, including: adjusting one or more of a temperature of a substrate, a duration of one or more temporally separated vapor phase pulses, a ratio of a tungsten precursor to a titanium precursor, or a pressure of a reaction to tune a work function of a p-metal work function nitride film to a desired p-work function, and contacting the substrate with temporally separated vapor phase pulses of the tungsten precursor, the titanium precursor, and a reactive gas to form a p-metal work function nitride film thereon having the desired p-work function.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: May 25, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Guoqiang Jian, Wei Tang, Chi-Chou Lin, Paul Ma, Yixiong Yang, Mei Chang, Wenyi Liu
  • Publication number: 20210134972
    Abstract: Metal gate stacks and integrated methods of forming metal gate stacks are disclosed. Some embodiment comprise MoN as a PMOS work function material. Some embodiments comprise TiSiN as a high-? capping layer. Some embodiments provide improved PMOS bandedge performance. Some embodiments provide improved PMOS bandedge performance with reduced EOT penalty.
    Type: Application
    Filed: November 4, 2020
    Publication date: May 6, 2021
    Inventors: Yixiong Yang, Jacqueline S. Wrench, Srinivas Gandikota, Yongjing Lin, Steven C.H. Hung, Shih Chung Chen, Haoyan Sha, Chi-Chou Lin
  • Publication number: 20210104563
    Abstract: An ultra-thin package structure for an integrated circuit having sensing functions is disclosed. It includes: a first substrate layer, having a first top side and a first bottom side, wherein a plurality of conductive traces are formed on the first top side and the first bottom side; an integrated circuit, having at least one gold-plated die pad on the top side thereof, wherein the at least one gold-plated die pad is connected to the corresponding conductive trace on the first bottom side of the first substrate layer by SMT; a second substrate layer, having a second top side and a second bottom side, wherein a plurality of conductive traces are formed on the second bottom side, and some portions of the conductive traces are covered by solder mask while other portions are exposed externally; and a filling material layer, formed between the first and the second substrate layer with the integrated circuit therebetween.
    Type: Application
    Filed: October 2, 2019
    Publication date: April 8, 2021
    Inventors: Chi-Chou LIN, Zheng Ping HE
  • Patent number: 10963546
    Abstract: A biometric security device for digital key storing is disclosed. The biometric security device includes a biometric information fetching module and a processing module. The processing module has a nonvolatile storage unit and a processing unit. The nonvolatile storage unit includes a secure storage unit and a general storage unit. The biometric security device with a secure electronic key designed for storing secret data utilizes both TrustZoneā„¢ technology (or similar technology) and biometric authentication. Thus, it can provide the flexibility for multiple users or applications to use the biometric security device or any equipment the biometric security device mounted in without compromising the safeguard of the data stored therein.
    Type: Grant
    Filed: April 9, 2018
    Date of Patent: March 30, 2021
    Assignee: SunASIC Technologies, Inc.
    Inventors: Chi Chou Lin, Zheng Ping He
  • Patent number: 10879081
    Abstract: Methods and apparatus for reducing and eliminating defects in tungsten film are disclosed herein. In the present disclosure, reducing or eliminating oxidation of a first surface of a tungsten film having a predetermined first thickness disposed upon a substrate and within a plurality of trenches is disclosed. The plurality of trenches include a predetermined depth, and a width of less than 20 nanometers. The predetermined first thickness of the tungsten film is substantially uniform throughout the plurality of trenches such that the predetermined first thickness of the tungsten film does not substantially change to a second thickness when the first surface is contacted with air or oxygen.
    Type: Grant
    Filed: November 20, 2018
    Date of Patent: December 29, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Guoqiang Jian, Wei Tang, Chi-Chou Lin, Paul F. Ma, Kai Wu, Vikash Banthia, Mei Chang, Jia Ye, Wenyu Zhang, Jing Zhou