Abstract: A device includes first and second gate structures respectively extending across the first and second fins, and a gate isolation plug between a longitudinal end of the first gate structure and a longitudinal end of the second gate structure. The gate isolation plug comprises a first dielectric layer and a second dielectric layer over the first dielectric layer. The first dielectric layer has an upper portion and a lower portion below the upper portion. The upper portion has a thickness smaller than a thickness of the lower portion of the first dielectric layer.

Abstract: Various solutions for extended reality (XR) enhancement in mobile communications are described. An apparatus establishes a communication with a network node of a wireless network. The apparatus performs an operation with respect to XR-related computation offloading from a user end to result in XR enhancement at the user end.

Abstract: The present invention provides an unique ID electronic (UID) tag for a tire, which is suitable to be mounted on a surface of tire or embedded in a tire, comprising: a tag unit; a pliable protective layer; and a vulcanizable bonding layer. The pliable protective layer provided on two opposite sides of the tag unit. The vulcanizable bonding layer provided on one or each of the two opposite sides of the pliable protective layer to bond the UID tag tightly to the tire during a vulcanization process. Further, the tag unit comprises a circuit substrate provided with an antenna circuit, and an integrated circuit (IC) chip electrically connected to the antenna circuit.

Abstract: The present invention provides an unique ID electronic (UM) tag for a tire, which is suitable to be mounted on a surface of tire or embedded in a tire, comprising: a tag unit; a pliable protective layer; and a vuicanizable bonding layer. The pliable protective layer provided on two opposite sides of the tag unit. The vulcanizable bonding layer provided on one or each of the two opposite sides of the pliable protective layer to bond the UID tag tightly to the tire during a vulcanization process. Further, the tag unit comprises a circuit substrate provided with an antenna circuit, and an integrated circuit (IC) chip electrically connected to the antenna circuit.

Abstract: A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate encircling the first insulation layer. Each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the substrate.

Abstract: A method of forming a device includes printing conductive patterns on a dielectric sheet to form a pre-ink-printed sheet, and bonding the pre-ink-printed sheet onto a side of a substrate. The conductive feature includes a through-substrate via extending from a first major side of the substrate to a second major side of the substrate opposite the first major side. A conductive paste is then applied to electrically couple conductive patterns to a conductive feature in the substrate.

Abstract: A method of forming an interposer includes providing a semiconductor substrate, the semiconductor substrate having a front surface and a back surface opposite the front surface; forming one or more through-silicon vias (TSVs) extending from the front surface into the semiconductor substrate; forming an inter-layer dielectric (ILD) layer overlying the front surface of the semiconductor substrate and the one or more TSVs; and forming an interconnect structure in the ILD layer, the interconnect structure electrically connecting the one or more TSVs to the semiconductor substrate.

Abstract: A method of forming a device includes printing conductive patterns on a dielectric sheet to form a pre-ink-printed sheet, and bonding the pre-ink-printed sheet onto a side of a substrate. The conductive feature includes a through-substrate via extending from a first major side of the substrate to a second major side of the substrate opposite the first major side. A conductive paste is then applied to electrically couple conductive patterns to a conductive feature in the substrate.

Abstract: A method of forming a device includes printing conductive patterns on a dielectric sheet to form a pre-ink-printed sheet, and bonding the pre-ink-printed sheet onto a side of a substrate. The conductive feature includes a through-substrate via extending from a first major side of the substrate to a second major side of the substrate opposite the first major side. A conductive paste is then applied to electrically couple conductive patterns to a conductive feature in the substrate.

Abstract: A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate encircling the first insulation layer. Each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the substrate.

Abstract: A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate encircling the first insulation layer. Each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the substrate.

Abstract: A method of forming an interposer includes providing a semiconductor substrate, the semiconductor substrate having a front surface and a back surface opposite the front surface; forming one or more through-silicon vias (TSVs) extending from the front surface into the semiconductor substrate; forming an inter-layer dielectric (ILD) layer overlying the front surface of the semiconductor substrate and the one or more TSVs; and forming an interconnect structure in the ILI) layer, the interconnect structure electrically connecting the one or more TSVs to the semiconductor substrate.

Abstract: An under-bump metallization (UBM) structure for a semiconductor device is provided. The UBM structure has a center portion and extensions extending out from the center portion. The extensions may have any suitable shape, including a quadrangle, a triangle, a circle, a fan, a fan with extensions, or a modified quadrangle having a curved surface. Adjacent UBM structures may have the respective extensions aligned or rotated relative to each other. Flux may be applied to a portion of the extensions to allow an overlying conductive bump to adhere to a part of the extensions.

Abstract: A device includes a substrate having a front surface and a back surface opposite the front surface. A capacitor is formed in the substrate and includes a first capacitor plate; a first insulation layer encircling the first capacitor plate; and a second capacitor plate encircling the first insulation layer. Each of the first capacitor plate, the first insulation layer, and the second capacitor plate extends from the front surface to the back surface of the substrate.

Abstract: A method of forming a device includes printing conductive patterns on a dielectric sheet to form a pre-ink-printed sheet, and bonding the pre-ink-printed sheet onto a side of a substrate. The conductive feature includes a through-substrate via extending from a first major side of the substrate to a second major side of the substrate opposite the first major side. A conductive paste is then applied to electrically couple conductive patterns to a conductive feature in the substrate.

Abstract: An under-bump metallization (UBM) structure for a semiconductor device is provided. The UBM structure has a center portion and extensions extending out from the center portion. The extensions may have any suitable shape, including a quadrangle, a triangle, a circle, a fan, a fan with extensions, or a modified quadrangle having a curved surface. Adjacent UBM structures may have the respective extensions aligned or rotated relative to each other. Flux may be applied to a portion of the extensions to allow an overlying conductive bump to adhere to a part of the extensions.

Abstract: A method is disclosed for controlling the sheet resistance of copper trenches formed on semiconductor wafers. The method includes forming a plurality of copper-filled trenches on a wafer, measuring the sheet resistance of each of the plurality of copper-filled trenches, and comparing the measured sheet resistance values to a predetermined sheet resistance value. Photolithography steps performed on subsequent wafers are adjusted according to a difference between the measured sheet resistance values and the predetermined value. In one embodiment, this adjustment takes the form of adjusting a photolithographic extension exposure energy to thereby adjust the cross-section of the resulting trenches.

Abstract: A method for improving within-wafer uniformity is provided. The method includes forming an electrical component by a first process step and a second process step, wherein the electrical component has a target electrical parameter. The method includes providing a first plurality of production tools for performing the first process step; providing a second plurality of production tools for performing the second process step; providing a wafer; performing the first process step on the wafer using one of the first plurality of production tools; and selecting a first route including a first production tool from the second plurality of production tools. A within-wafer uniformity of the target electrical parameter on the wafer manufactured by the first route is greater than a second route including a second production tool in the second plurality of production tools.

Abstract: A method is disclosed for controlling the sheet resistance of copper trenches formed on semiconductor wafers. The method includes forming a plurality of copper-filled trenches on a wafer, measuring the sheet resistance of each of the plurality of copper-filled trenches, and comparing the measured sheet resistance values to a predetermined sheet resistance value. Photolithography steps performed on subsequent wafers are adjusted according to a difference between the measured sheet resistance values and the predetermined value. In one embodiment, this adjustment takes the form of adjusting a photolithographic extension exposure energy to thereby adjust the cross-section of the resulting trenches.

Abstract: A method of forming an interposer includes providing a semiconductor substrate, the semiconductor substrate having a front surface and a back surface opposite the front surface; forming one or more through-silicon vias (TSVs) extending from the front surface into the semiconductor substrate; forming an inter-layer dielectric (ILD) layer overlying the front surface of the semiconductor substrate and the one or more TSVs; and forming an interconnect structure in the ILD layer, the interconnect structure electrically connecting the one or more TSVs to the semiconductor substrate.