Abstract: A metal-insulator-metal (MIM) capacitor structure and a method for manufacturing the same. The method includes a step hereinafter. A 5-layered dual-dielectric structure is provided on a substrate. The 5-layered dual-dielectric structure includes a bottom metal layer, a first dielectric layer, an intermediate metal layer, a second dielectric layer and a top metal layer in order. The first dielectric layer and the second dielectric layer have different thicknesses.

Abstract: A semiconductor apparatus including a stacked capacitance structure is provided. The stacked capacitance structure includes a first inner metal layer having a first pad area adjacent to an edge of the first inner metal layer, a first insulating layer disposed on the first inner metal layer and exposing the first pad area, a second inner metal layer disposed on the first insulating layer and having a second pad area adjacent to an edge of the second inner metal layer, a second insulating layer disposed on the second inner metal layer and exposing the second pad area, and a third inner metal layer covering the second inner metal layer and including at least one first slit. The first pad area and the second pad area include a plurality of pads. The first slit corresponds to the second pad area, such that the pads on the second pad area are exposed.

Abstract: A semiconductor apparatus including a stacked capacitance structure is provided. The stacked capacitance structure includes a first inner metal layer having a first pad area adjacent to an edge of the first inner metal layer, a first insulating layer disposed on the first inner metal layer and exposing the first pad area, a second inner metal layer disposed on the first insulating layer and having a second pad area adjacent to an edge of the second inner metal layer, a second insulating layer disposed on the second inner metal layer and exposing the second pad area, and a third inner metal layer covering the second inner metal layer and including at least one first slit. The first pad area and the second pad area include a plurality of pads. The first slit corresponds to the second pad area, such that the pads on the second pad area are exposed.

Abstract: A chip-stack interposer structure including a passive device is described, including an interposing layer, a capacitor, a first contact and a second contact. The capacitor is embedded in or disposed on the interposing layer, including a first electrode, a second electrode and a dielectric layer between the first and the second electrodes. The first contact is connected with the first electrode. The second contact is connected with the second electrode. The first electrode and the second electrode are disposed at the same side of the interposing layer or at different sides of the interposing layer.

Abstract: An integrated circuit includes a capacitor and a non-inductive resistor. A substrate has a capacitor area and a resistor area. A patterned stacked structure including a bottom conductive layer, an insulating layer and a top conductive layer from bottom to top is sandwiched by a first dielectric layer and a second dielectric layer disposed on the substrate. A first metal plug and a second metal plug contact the top conductive layer and the bottom conductive layer of the capacitor area respectively, thereby the patterned stacked structure in the capacitor area constituting the capacitor. A third metal plug and a fourth metal plug contact the bottom conductive layer and the top conductive layer of the resistor area respectively, and a fifth metal plug contacts the bottom conductive layer and the top conductive layer of the resistor area simultaneously, thereby the patterned stacked structure in the resistor area constituting the non-inductive resistor.

Abstract: A method for fabricating through silicon via (TSV) structure is disclosed. The method includes the steps of: providing a substrate; forming a through-silicon via (TSV) in the substrate; depositing a liner in the TSV; removing the liner in a bottom of the TSV; and filling a first conductive layer in the TSV for forming a TSV structure.

Abstract: A method for removing residual color photoresist material from a substrate after photoresist development. The method washes the substrate with a high-pressure jet of de-ionized water that contains an activated interface agent. A second method of removing the residual photoresist material bombards the substrate with oxygen plasma for a brief period so that the residual photoresist material is polarized and then rinses the substrate with de-ionized water.

Abstract: A method for removing residual color photoresist material from a substrate after photoresist development. The method washes the substrate with a high-pressure jet of de-ionized water that contains an activated interface agent. A second method of removing the residual photoresist material bombards the substrate with oxygen plasma for a brief period so that the residual photoresist material is polarized and then rinses the substrate with de-ionized water.

Abstract: The invention proposes a method of predicting the curvature radius of the microlens. By adjusting a spin speed of spin coating and exposure energy during a photolithography step, a volume of the patterned microlens material layer is controlled. Then a lens-forming step is performed to transform the patterned microlens material layer into a microlens. After measuring a diameter of the microlens, the volume of the microlens material layer is multiplied by a contraction coefficient to calculate a volume of the microlens. Then the diameter and the volume of the microlens are used to calculate a curvature radius.

Abstract: An apparatus for removing photo-resist. The apparatus comprises carriers for carrying a wafer, hot plates to remove residue solvent on the wafer, a cooling plate to decrease the wafer temperature, an reverse unit to turn over the wafer, a development unit to develop and remove photo-resist on the wafer, a top scrubbing unit to clean a top side of the wafer, and a back scrubbing unit to clean a back side of the wafer.

Abstract: A method of removing photo-resist. Acetone, thinner, and deionized water for scrubbing a wafer are used to clean a wafer on which a photo-resist layer is formed, so that thinner and deionized water are mutually dissolvable with acetone as medium. The photo-resist layer is then removed.

Abstract: A recess-free buffer layer is formed on a semiconductor substrate having island structures formed thereon. A first buffer layer is formed over the substrate and the island structures. A first reflow process is then performed for reflowing the first buffer layer into spaces between the island structures. A portion of the first buffer layer located outside the spaces is removed. A second buffer layer is formed over the first buffer layer and the island structures. The method can further include a step of performing a second thermal soft-bake process to the second buffer layer. The second buffer layer can also be patterned after the soft-bake process.

Abstract: A method for detecting defects comprises scanning a clean blank wafer for figuring out the quantity and locations of particles; then, scanning the wafer again after performing coating, exposure, and development processes on the wafer; comparing the two scanning results for figuring out the locations of the defects and calculating quantities of the defects by checking the patterns and colors, and then to obtain the quantities and types of the defects in mechanisms and photoresist respectively.

Abstract: The invention provides a method of avoiding peeling on the wafer edge and the mark number. The method uses a design rule to expose the multi-layer on a wafer. The limit and the scope of the exposed distance are taken to ensure the polysilicon layers and the metal layers are covered by the dielectric layer after exposure. The polysilicon layers or the metal layers don't unclothe from the overlarge distance at the exposed dielectric layer, so the next structure formed on the exposed dielectric layer doesn't peeling from contacting with the polysilicon layer or the metal layer. The invention avoids to contaminate the wafer and the machine after the particles forming from peeling.

Abstract: A method for applying photoresist on a wafer is disclosed. The method comprises: lowering the temperature of the photoresist, and dispensing the photoresist on a portion of the wafer, where the wafer is supported by a spinner chuck and is rotated at a low speed. Thereafter, spreading the photoresist on the wafer by rotating the wafer at a high speed. Finally, planarizing the photoresist by rotating the wafer at a medium speed greater than or equal to the low speed in the dispensing step and less than or equal to the high speed in the spreading step.