Patents by Inventor Chi-Feng Lin

Chi-Feng Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12341101
    Abstract: A method for forming a semiconductor device structure is provided. The method includes removing a portion of a dielectric layer to form a trench in the dielectric layer. The method includes forming a barrier layer in the trench. The method includes forming a seed layer in the trench and over the barrier layer. The seed layer is doped with manganese. The method includes annealing the seed layer in a first process gas including a first hydrogen gas. A volume ratio of the first hydrogen gas to the first process gas ranges from about 50% to about 100%, and the manganese diffuses from the seed layer to the barrier layer during the annealing of the seed layer in the first process gas.
    Type: Grant
    Filed: May 11, 2022
    Date of Patent: June 24, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cai-Ling Wu, Hsiu-Wen Hsueh, Chii-Ping Chen, Po-Hsiang Huang, Chi-Feng Lin
  • Patent number: 12334397
    Abstract: A method includes forming a first conductive feature, depositing a graphite layer over the first conductive feature, patterning the graphite layer to form a graphite conductive feature, depositing a dielectric spacer layer on the graphite layer, depositing a first dielectric layer over the dielectric spacer layer, planarizing the first dielectric layer, forming a second dielectric layer over the first dielectric layer, and forming a second conductive feature in the second dielectric layer. The second conductive feature is over and electrically connected to the graphite conductive feature.
    Type: Grant
    Filed: July 21, 2021
    Date of Patent: June 17, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shu-Cheng Chin, Chih-Yi Chang, Wei Hsiang Chan, Chih-Chien Chi, Chi-Feng Lin, Hung-Wen Su
  • Publication number: 20250183161
    Abstract: A method of making semiconductor device includes forming an insulating layer. The method further includes patterning the insulating layer to define a via opening and a conductive line opening. The method further includes forming a via in the via opening. The method further includes forming a conductive line in the conductive line opening. Forming the conductive line includes forming a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and forming a conductive fill, wherein the first liner layer surrounds the conductive fill.
    Type: Application
    Filed: February 13, 2025
    Publication date: June 5, 2025
    Inventors: Shu-Cheng CHIN, Yao-Min LIU, Hung-Wen SU, Chih-Chien CHI, Chi-Feng LIN
  • Patent number: 12315764
    Abstract: A barrier layer is selectively formed on a bottom surface of a recess (e.g., in which a back end of line (BEOL) conductive structure will be formed) using a combination of flash physical vapor deposition with atomic layer deposition. Additionally, a ruthenium liner is selectively deposited on sidewalls of the BEOL conductive structure using a blocking material. Accordingly, the barrier layer prevents diffusion of metal ions from the BEOL conductive structure and is thinner at the bottom surface as compared to the sidewalls in order to reduce contact resistance. Additionally, the ruthenium liner improves copper flow into the BEOL conductive structure and is thinner at the bottom surface in order to further reduce contact resistance.
    Type: Grant
    Filed: January 12, 2022
    Date of Patent: May 27, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shu-Cheng Chin, Chih-Chien Chi, Chi-Feng Lin
  • Publication number: 20250167046
    Abstract: Conductive vias, semiconductor devices with conductive vias, and methods for fabricating semiconductor devices are provided. A conductive via includes a first end and a second end; a first portion adjacent to the first end; a second portion adjacent to the second; and a middle portion located between the first portion and the second portion, wherein the conductive via is comprised of metal grains, the metal grains in the first portion have a first grain size; the metal grains in the second portion have a second grain size; the metal grains in the middle portion have a third grain size; the first grain size is greater than the third grain size; and the second grain size is greater than the third grain size.
    Type: Application
    Filed: November 20, 2023
    Publication date: May 22, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Pang Kuo, Tzu-Hung Yang, I-Hsin Tseng, Jung-Hsuan Su, Wei Hsiang Chan, Chi-Feng Lin
  • Patent number: 12237261
    Abstract: A semiconductor device includes an insulating layer, wherein the insulating layer has a via opening and a conductive line opening. The semiconductor device further includes a via in the via opening. The semiconductor device further includes a conductive line in the conductive line opening. The conductive line includes a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and a conductive fill, wherein the first liner layer surrounds the conductive fill.
    Type: Grant
    Filed: May 4, 2023
    Date of Patent: February 25, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Cheng Chin, Yao-Min Liu, Hung-Wen Su, Chih-Chien Chi, Chi-Feng Lin
  • Publication number: 20240413087
    Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.
    Type: Application
    Filed: July 31, 2024
    Publication date: December 12, 2024
    Inventors: Shu-Cheng Chin, Ming-Yuan Gao, Chen-Yi Niu, Yen-Chun Lin, Hsin-Ying Peng, Chih-Hsiang Chang, Pei-Hsuan Lee, Chi-Feng Lin, Chih-Chien Chi, Hung-Wen Su
  • Patent number: 12165975
    Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: December 10, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Cheng Chin, Ming-Yuan Gao, Chen-Yi Niu, Yen-Chun Lin, Hsin-Ying Peng, Chih-Hsiang Chang, Pei-Hsuan Lee, Chi-Feng Lin, Chih-Chien Chi, Hung-Wen Su
  • Publication number: 20240387382
    Abstract: Implementations of low-resistance copper interconnects and manufacturing techniques for forming the low-resistance copper interconnects described herein may achieve low contact resistance and low sheet resistance by decreasing tantalum nitride (TaN) liner/film thickness (or eliminating the use of tantalum nitride as a copper diffusion barrier) and using ruthenium (Ru) and/or zinc silicon oxide (ZnSiOx) as a copper diffusion barrier, among other examples. The low contact resistance and low sheet resistance of the copper interconnects described herein may increase the electrical performance of an electronic device including such copper interconnects by decreasing the resistance/capacitance (RC) time constants of the electronic device and increasing signal propagation speeds across the electronic device, among other examples.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Shu-Cheng CHIN, Chih-Chien CHI, Chi-Feng LIN
  • Publication number: 20240387259
    Abstract: A barrier layer is selectively formed on a bottom surface of a recess (e.g., in which a back end of line (BEOL) conductive structure will be formed) using a combination of flash physical vapor deposition with atomic layer deposition. Additionally, a ruthenium liner is selectively deposited on sidewalls of the BEOL conductive structure using a blocking material. Accordingly, the barrier layer prevents diffusion of metal ions from the BEOL conductive structure and is thinner at the bottom surface as compared to the sidewalls in order to reduce contact resistance. Additionally, the ruthenium liner improves copper flow into the BEOL conductive structure and is thinner at the bottom surface in order to further reduce contact resistance.
    Type: Application
    Filed: July 30, 2024
    Publication date: November 21, 2024
    Inventors: Shu-Cheng CHIN, Chih-Chien CHI, Chi-Feng LIN
  • Publication number: 20240379436
    Abstract: The present disclosure provides an exemplary semiconductor structure that includes a substrate having a conductive feature disposed in a top portion of the substrate, a metal line above the substrate and in electrical coupling with the conductive feature, a dielectric feature disposed on a sidewall of the metal line, an etch stop layer disposed on the dielectric feature and the meta line, and a via extending through the etch stop layer and in physical contact with top surfaces of the dielectric feature and the metal line. The metal line has a first metal, and the via has a second metal different from the first metal. The top surface of the dielectric feature is higher than the top surface of the metal line.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Cai-Ling Wu, Hsiu-Wen Hsueh, Chii-Ping Chen, Po-Hsiang Huang, Chi-Feng Lin, Neng-Jye Yang
  • Publication number: 20240379430
    Abstract: A method includes forming a first conductive feature, depositing a graphite layer over the first conductive feature, patterning the graphite layer to form a graphite conductive feature, depositing a dielectric spacer layer on the graphite layer, depositing a first dielectric layer over the dielectric spacer layer, planarizing the first dielectric layer, forming a second dielectric layer over the first dielectric layer, and forming a second conductive feature in the second dielectric layer. The second conductive feature is over and electrically connected to the graphite conductive feature.
    Type: Application
    Filed: July 24, 2024
    Publication date: November 14, 2024
    Inventors: Shu-Cheng Chin, Chih-Yi Chang, Wei Hsiang Chan, Chih-Chien Chi, Chi-Feng Lin, Hung-Wen Su
  • Publication number: 20240321733
    Abstract: An interconnection structure and methods of forming the same are described. The interconnection structure includes a dielectric layer, a dielectric material disposed over the dielectric layer, and first and second conductive features disposed in the dielectric material. The first and second conductive features each has rounded top corners, the first conductive feature has a first width and a first height, and the second conductive feature has a second width substantially less than the first width and a second height substantially the same as the first height. The structure further includes an etch stop layer disposed on the first and second conductive features and third and fourth conductive features disposed in the dielectric material and the etch stop layer. The third conductive feature is in contact with the first conductive feature, and the fourth conductive feature is in contact with the second conductive feature.
    Type: Application
    Filed: June 14, 2023
    Publication date: September 26, 2024
    Inventors: Chia-Pang KUO, Jo-Lin LAN, Chun Hsiang YANG, Ming-Yuan GAO, Chi-Feng LIN
  • Publication number: 20240304551
    Abstract: Devices with aluminum structures and methods of fabrication are provided. An exemplary device includes an interconnect structure and an aluminum structure electrically connected to the interconnect structure. The aluminum structure includes a first aluminum layer, a migration barrier layer over the first aluminum layer, and a second aluminum layer over the migration barrier layer.
    Type: Application
    Filed: March 7, 2023
    Publication date: September 12, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Pang Kuo, Sean Yang, Yue-Guo Lin, Tsai Hsi-Chen, Chi-Feng Lin, Hung-Wen Su
  • Publication number: 20240282628
    Abstract: A method of forming a semiconductor structure includes forming a seed layer on a substrate, forming a photoresist layer on the seed layer with a first opening wider than a second opening, performing an electroplating process with a first plating current to grow a bottom portion of a first metal line in the first opening and a bottom portion of a second metal line in the second opening, continuing the electroplating process with a second plating current that is larger than the first plating current to grow a top portion of the first metal line and a top portion of the second metal line, removing the photoresist layer to expose a portion of the seed layer, and removing the exposed portion of the seed layer.
    Type: Application
    Filed: July 25, 2023
    Publication date: August 22, 2024
    Inventors: Dian-Hau CHEN, Chen-Chiu HUANG, Hsiang-Ku SHEN, ShuFang CHEN, Ying-Yao LAI, Wen-Ling CHANG, Chi-Feng LIN, Peng-Chung JANGJIAN, Jo-Lin LAN, Fang-I Chih
  • Patent number: 11996361
    Abstract: A method of making a semiconductor device includes etching an insulating layer to form a first opening and a second opening. The method further includes depositing a conductive material in the first opening. The method further includes performing a surface modification process on the conductive material. The method further includes depositing, after the surface modification process, a first liner layer in the second opening, wherein the first liner layer extends over the conductive material and the insulating layer. The method further includes depositing a conductive fill over the first liner layer, wherein the conductive fill includes a different material from the conductive material.
    Type: Grant
    Filed: August 10, 2022
    Date of Patent: May 28, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Shu-Cheng Chin, Yao-Min Liu, Hung-Wen Su, Chih-Chien Chi, Chi-Feng Lin
  • Publication number: 20230369226
    Abstract: A method for forming a semiconductor device structure is provided. The method includes removing a portion of a dielectric layer to form a trench in the dielectric layer. The method includes forming a barrier layer in the trench. The method includes forming a seed layer in the trench and over the barrier layer. The seed layer is doped with manganese. The method includes annealing the seed layer in a first process gas including a first hydrogen gas. A volume ratio of the first hydrogen gas to the first process gas ranges from about 50% to about 100%, and the manganese diffuses from the seed layer to the barrier layer during the annealing of the seed layer in the first process gas.
    Type: Application
    Filed: May 11, 2022
    Publication date: November 16, 2023
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cai-Ling WU, Hsiu-Wen HSUEH, Chii-Ping CHEN, Po-Hsiang HUANG, Chi-Feng LIN
  • Publication number: 20230361039
    Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material.
    Type: Application
    Filed: July 13, 2023
    Publication date: November 9, 2023
    Inventors: Shu-Cheng Chin, Ming-Yuan Gao, Chen-Yi Niu, Yen-Chun Lin, Hsin-Ying Peng, Chih-Hsiang Chang, Pei-Hsuan Lee, Chi-Feng Lin, Chih-Chien Chi, Hung-Wen Su
  • Publication number: 20230275019
    Abstract: A semiconductor device includes an insulating layer, wherein the insulating layer has a via opening and a conductive line opening. The semiconductor device further includes a via in the via opening. The semiconductor device further includes a conductive line in the conductive line opening. The conductive line includes a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and a conductive fill, wherein the first liner layer surrounds the conductive fill.
    Type: Application
    Filed: May 4, 2023
    Publication date: August 31, 2023
    Inventors: Shu-Cheng CHIN, Yao-Min LIU, Hung-Wen SU, Chih-Chien CHI, Chi-Feng LIN
  • Patent number: 11742290
    Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: August 29, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Shu-Cheng Chin, Ming-Yuan Gao, Chen-Yi Niu, Yen-Chun Lin, Hsin-Ying Peng, Chih-Hsiang Chang, Pei-Hsuan Lee, Chi-Feng Lin, Chih-Chien Chi, Hung-Wen Su