Abstract: A gas detection and cleaning system for a vehicle is disclosed and includes an external modular base, a gas detection module and a cleaning device. The gas detection module is connected to a first external connection port of the external modular base to detect a gas in the vehicle and output the information datum. The information datum is transmitted through the first external connection port to a driving and controlling module of the external modular base, processed and converted into an actuation information datum for being externally outputted through a second external connection port of the external modular base. The cleaning device is connected with the second external connection port through an external port to receive the actuation information datum outputted from the second external connection port to actuate or close the cleaning device.

Abstract: A blood pressure detection device manufactured by a semiconductor process includes a substrate, a microelectromechanical element, a gas-pressure-sensing element, a driving-chip element, an encapsulation layer and a valve layer. The substrate includes inlet apertures. The microelectromechanical element and the gas-pressure-sensing element are stacked and integrally formed on the substrate. The encapsulation layer is encapsulated and positioned on the substrate. A flowing-channel space is formed above the microelectromechanical element and the gas-pressure-sensing element. The encapsulation layer includes an outlet aperture in communication with an airbag. The driving-chip element controls the microelectromechanical element, the gas-pressure-sensing element and valve units to transport gas.

Abstract: A gas detection purification device is disclosed and includes a main body, a purification unit, a gas guider, a gas detection module and a controlling-driving module. The main body includes an inlet, an outlet, an external socket and a gas-flow channel disposed between the inlet and the outlet. The purification unit is disposed in the gas-flow channel for filtering gas introduced through the gas-flow channel. The gas guider is disposed in the gas channel and located at a side of the purification unit. The gas is inhaled through the inlet, flows through the purification unit and is discharged out through the outlet. The gas detection module is plugged into or detached from the external socket. The controlling driving module is disposed within the main body and electrically connected to the gas guider to control the operation of the gas guider in an enabled state and a disabled state.

Abstract: A method for operating a conveying system is provided. An overhead hoist transport (OHT) vehicle is provided, wherein the OHT vehicle includes a gripping member configured to grip and hold a carrier, and a receiver configured to receive a signal. The signal is transmitted to the receiver of the OHT vehicle. The OHT vehicle is moved toward the carrier, and the carrier is gripped by the gripping member of the OHT vehicle. A lifting force is determined based on a weight of a carrier, a number of workpieces in the carrier, or a vertical distance between the OHT vehicle and the carrier, and the lifting force is applied to the carrier.

Abstract: A system for a semiconductor fabrication facility comprises a transporting tool configured to move a carrier, a first manufacturing tool configured to accept the carrier facing in a first direction, a second manufacturing tool configured to accept the carrier facing in the second direction, and an orientation tool. The carrier is moved to the orientation tool by the transporting tool prior to being moved to the first manufacturing tool or the second manufacturing tool by the transporting tool. The orientation tool rotates the carrier so that the carrier is accepted by the first manufacturing tool or the second manufacturing tool. The transporting tool, the first manufacturing tool, the second manufacturing tool and the orientation tool are physically separated from each other.

Abstract: A method for forming a semiconductor device structure is provided. The method includes removing a portion of a dielectric layer to form a trench in the dielectric layer. The method includes forming a barrier layer in the trench. The method includes forming a seed layer in the trench and over the barrier layer. The seed layer is doped with manganese. The method includes annealing the seed layer in a first process gas including a first hydrogen gas. A volume ratio of the first hydrogen gas to the first process gas ranges from about 50% to about 100%, and the manganese diffuses from the seed layer to the barrier layer during the annealing of the seed layer in the first process gas.

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material.

Abstract: A semiconductor device includes an insulating layer, wherein the insulating layer has a via opening and a conductive line opening. The semiconductor device further includes a via in the via opening. The semiconductor device further includes a conductive line in the conductive line opening. The conductive line includes a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and a conductive fill, wherein the first liner layer surrounds the conductive fill.

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

Abstract: The present invention is directed to nanoparticles comprising: (a) an inner core comprising oligomeric (?)-epigallocatechin gallate (OEGCG), (b) an outer core comprising a polyethylene glycol-epigallocatechin gallate conjugate (PEG-EGCG), and (c) a protein molecule of a drug substance encapsulated in the inner core; wherein at least 70% of the nanoparticles have a diameter between 50-300 nm. The present invention also provides a process for preparing the nanoparticles. The present invention further provides a method of treating cancer by administering to a subject in need thereof the nanoparticles of the present invention, in an amount effective to treat cancer.

Abstract: A barrier layer is selectively formed on a bottom surface of a recess (e.g., in which a back end of line (BEOL) conductive structure will be formed) using a combination of flash physical vapor deposition with atomic layer deposition. Additionally, a ruthenium liner is selectively deposited on sidewalls of the BEOL conductive structure using a blocking material. Accordingly, the barrier layer prevents diffusion of metal ions from the BEOL conductive structure and is thinner at the bottom surface as compared to the sidewalls in order to reduce contact resistance. Additionally, the ruthenium liner improves copper flow into the BEOL conductive structure and is thinner at the bottom surface in order to further reduce contact resistance.

Abstract: A semiconductor device includes an insulating layer, wherein the insulating layer has a via opening and a conductive line opening. The semiconductor device further includes a via in the via opening, wherein the via includes a first conductive material. The semiconductor device further includes a conductive line in the conductive line opening. The conductive line includes a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and a conductive fill comprising a second conductive material different from the first conductive material.

Abstract: A blocking material is selectively deposited on a bottom surface of a back end of line (BEOL) conductive structure such that a barrier layer is selectively deposited on sidewalls of the BEOL conductive structure but not the bottom surface. The blocking material is etched such that copper from a conductive structure underneath is exposed, and a ruthenium layer is deposited on the barrier layer but less ruthenium is deposited on the exposed copper. Accordingly, the barrier layer prevents diffusion of metal ions from the BEOL conductive structure and is substantially absent from the bottom surface as compared to the sidewalls in order to reduce contact resistance. Additionally, the ruthenium layer reduces surface roughness within the BEOL conductive structure and is thinner at the bottom surface as compared to the sidewalls in order to reduce contact resistance.

Abstract: The present disclosure provides a method of forming an interconnect structure. The method includes forming a metal layer over a substrate, the metal layer including a first metal; forming a capping layer on the metal layer; patterning the capping layer and the metal layer, thereby forming trenches in the metal layer; depositing a first dielectric layer in the trenches; removing the capping layer, resulting in the first dielectric layer protruding from a top surface of the metal layer; depositing a second dielectric layer over the first dielectric layer and the metal layer; forming an opening in the second dielectric layer, thereby partially exposing the top surface of the metal layer; and forming a conductive feature in the opening and in electrical coupling with the metal layer, the conductive feature including a second metal.

Abstract: A method of making a semiconductor device includes etching an insulating layer to form a first opening and a second opening. The method further includes depositing a conductive material in the first opening. The method further includes performing a surface modification process on the conductive material. The method further includes depositing, after the surface modification process, a first liner layer in the second opening, wherein the first liner layer extends over the conductive material and the insulating layer. The method further includes depositing a conductive fill over the first liner layer, wherein the conductive fill includes a different material from the conductive material.

Abstract: A method includes forming a first conductive feature, depositing a graphite layer over the first conductive feature, patterning the graphite layer to form a graphite conductive feature, depositing a dielectric spacer layer on the graphite layer, depositing a first dielectric layer over the dielectric spacer layer, planarizing the first dielectric layer, forming a second dielectric layer over the first dielectric layer, and forming a second conductive feature in the second dielectric layer. The second conductive feature is over and electrically connected to the graphite conductive feature.

Abstract: A method of manufacturing an interconnect structure includes forming an opening through a dielectric layer. The opening exposes a top surface of a first conductive feature. The method further includes forming a barrier layer on sidewalls of the opening, passivating the exposed top surface of the first conductive feature with a treatment process, forming a liner layer over the barrier layer, and filling the opening with a conductive material. The liner layer may include ruthenium.

Abstract: A semiconductor device includes an insulating layer, wherein the insulating layer has a via opening and a conductive line opening. The semiconductor device further includes a via in the via opening, wherein the via includes a first conductive material. The semiconductor device further includes a conductive line in the conductive line opening. The conductive line includes a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and a conductive fill comprising a second conductive material different from the first conductive material.

Abstract: Implementations of low-resistance copper interconnects and manufacturing techniques for forming the low-resistance copper interconnects described herein may achieve low contact resistance and low sheet resistance by decreasing tantalum nitride (TaN) liner/film thickness (or eliminating the use of tantalum nitride as a copper diffusion barrier) and using ruthenium (Ru) and/or zinc silicon oxide (ZnSiOx) as a copper diffusion barrier, among other examples. The low contact resistance and low sheet resistance of the copper interconnects described herein may increase the electrical performance of an electronic device including such copper interconnects by decreasing the resistance/capacitance (RC) time constants of the electronic device and increasing signal propagation speeds across the electronic device, among other examples.

Abstract: An anthracene material, an organic light emitting diode using the same, and a method for manufacturing the same, are provided. The organic light emitting diode includes a substrate, a first conducting layer, a hole transport layer, a light emitting layer, an electron transport layer, and a second conducting layer. The first conducting layer is disposed on the substrate. The hole transport layer is disposed on the first conducting layer. The light emitting layer having the anthracene material is disposed on the hole transport layer. The electron transport layer is disposed on the light emitting layer. The second conducting layer is disposed on the electron transport layer.