Abstract: Embodiments of the present disclosure relate to a system, a software application, and methods of digital lithography for semiconductor packaging. The method includes comparing positions of vias and via locations, generating position data based on the comparing the positions of vias and the via locations, providing the position data of the vias to a digital lithography device, updating a redistributed metal layer (RDL) mask pattern according to the position data such that RDL locations correspond to the positions of the vias, and projecting the RDL mask pattern with the digital lithography device.

Abstract: Methods and devices for determining whether a mobile device has been compromised. The mobile device has a managed portion of memory and an unmanaged portion of memory, a managed profile and an unmanaged profile, and the managed profile includes files stored in the managed portion of memory and the unmanaged profile includes files stored in the unmanaged portion of memory. The managed profile is governed by a device policy set by a remote administrator. File tree structure information for the unmanaged profile of the mobile device is obtained that details at least a portion of a tree-based structure of folders and files in the unmanaged portion of memory. It is determined from the file tree structure information that the mobile device has been compromised and, based on that determination, an action is taken.

Abstract: A laser leveling tool comprising: gesture control means comprises at least one sensor adapted to sense gestures and/or movements of a user; and a controller in communication with the gesture control means for receiving signals from the sensor and generating control commands for the tool based on the received signals, the control commands comprising at least ON/OFF states of laser beam patterns that the tool can project.

Abstract: The disclosure relates to a method for determining a profile section of an object and/or space by means of a 2D laser scanner having a laser rangefinder, including: recording mutually assignable distance measurement values and distance measurement directions by means of the laser rangefinder in a measuring plane traversed radially by a laser beam of the laser rangefinder, determining the profile section, from the distance measurement values and distance measurement directions, determining an angle of inclination of the measuring plane with respect to a reference plane, and correcting the profile section using the angle of inclination of the measuring plane. According to the disclosure, the angle of inclination of the measuring plane is determined by using the laser rangefinder. The disclosure also relates to a 2D laser scanner and to a system.

Abstract: A first device verification model is sent to a first agent on a first device providing at least a portion of the service. The first agent is able to monitor based on the first device verification model a parameter of the first device related to the service. A second device verification model is sent to a second agent on a second device providing at least a portion of the service, wherein the second agent is able to monitor based on the second device verification model a parameter of the second device related to the service. A report is received from the first agent of at least the parameter of the first device. A report is received from the second agent of at least the parameter of the second device. At least the parameter of the first device and at least the parameter of the second device are analyzed to determine whether the service is functioning as intended.

Abstract: A multi-stage pipelined Analog-to-Digital Converter (ADC) has an offset correction circuit embedded in the residue amplifier between stages. The offset corrector has a low-pass filter that filters the output of the residue amplifier, and the filtered offset is amplified and stored on an offset capacitor during an autozeroing phase of the residue amplifier. During an amplify phase of the residue amplifier, switches disconnect the amplifier from the offset capacitor and instead ground the input of the offset capacitor, and other switches connect the output terminal of the offset capacitor to the input of the residue amplifier. The offset stored on the offset capacitor is combined with the residue voltage from the first ADC stage's capacitor array and applied to an input of the residue amplifier to effectively subtract the detected offset. Two offset capacitors and sets of switches can be used to implement a differential offset corrector.

Abstract: A multiplication injection locked oscillator (MIILO) circuitry includes a ring injection locked oscillator (ILO) circuitry that outputs clock signals, a first switching circuitry and a second switching circuitry. The ring ILO circuitry includes a first path having first delay stages, and a second path having a second delay stages. The first switching circuitry is connected to the first path and a voltage supply node. The first switching circuitry receives a first control signal and a second control signal and selectively connects the voltage supply node to the first path. The second switching circuitry is connected to the second path and a reference voltage node. The second switching circuitry receives the first control signal and the second control signal and selectively connects the reference voltage node to the second path.

Abstract: A multi-stage pipelined Analog-to-Digital Converter (ADC) has an offset correction circuit embedded in the residue amplifier between stages. The offset corrector has a low-pass filter that filters the output of the residue amplifier, and the filtered offset is amplified and stored on an offset capacitor during an autozeroing phase of the residue amplifier. During an amplify phase of the residue amplifier, switches disconnect the amplifier from the offset capacitor and instead ground the input of the offset capacitor, and other switches connect the output terminal of the offset capacitor to the input of the residue amplifier. The offset stored on the offset capacitor is combined with the residue voltage from the first ADC stage's capacitor array and applied to an input of the residue amplifier to effectively subtract the detected offset. Two offset capacitors and sets of switches can be used to implement a differential offset corrector.

Abstract: A reference buffer has many legs each with an upper transistor, a lower transistor, and a resistor or current source as a tail device in series. The source or emitter of the upper (lower) transistor generates an upper (lower) reference voltage. This source follower transistor configuration has a low output impedance and high current. The gate or base of the upper (lower) transistors are driven by a first (second) control node. A control leg has an upper transistor, a lower transistor, and a tail device in series. The source and gate, or emitter and base, are connected together for the upper and lower transistors and generate the upper and lower control nodes. Alternately, the gate or base of the upper (lower) transistor is driven by an op amp receiving an upper (lower) bandgap voltage and the upper (lower) control node as negative feedback.

Abstract: A differential residue amplifier fits between Analog-to-Digital Converter (ADC) stages. Switched-Capacitor Common-Mode Feedback circuits determine voltage shifts. An AC-coupled input network uses switched capacitors to shift upward voltages of the differential inputs to the residue amplifier to apply to an upper pair of p-channel differential transistors with sources connected to the power supply. The AC-coupled input network also shifts downward in voltage the differential inputs to the residue amplifier to apply to a lower pair of n-channel differential transistors with grounded sources. The drains of the p-channel differential transistors connect to differential outputs through p-channel cascode transistors. N-channel cascode transistors connect the drains of the n-channel differential transistors to the differential outputs. The drains of differential transistors can be input to differential amplifiers to drive the gates of the cascode transistors for gain boosting.

Abstract: A reference buffer has many legs each with an upper transistor, a lower transistor, and a resistor or current source as a tail device in series. The source or emitter of the upper (lower) transistor generates an upper (lower) reference voltage. This source follower transistor configuration has a low output impedance and high current. The gate or base of the upper (lower) transistors are driven by a first (second) control node. A control leg has an upper transistor, a lower transistor, and a tail device in series. The source and gate, or emitter and base, are connected together for the upper and lower transistors and generate the upper and lower control nodes. Alternately, the gate or base of the upper (lower) transistor is driven by an op amp receiving an upper (lower) bandgap voltage and the upper (lower) control node as negative feedback.

Abstract: Clock generation circuitry includes quadrature locked loop circuitry having first injection locked oscillator circuitry, second injection locked oscillator circuitry, and XOR circuitry. The first injection locked oscillator circuitry receives a first input signal and a second input signal and outputs first clock signals. The first input signal and the second input signal correspond to a reference clock signal. The second injection locked oscillator circuitry is coupled to outputs of the first injection locked oscillator circuitry, and receives the first clock signals and generates second clock signals. The XOR circuitry receives the second clock signals and generates a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal. The frequencies of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are greater than the frequency of the reference clock signal.

Abstract: Examples described herein generally relate to communication between integrated circuit (IC) dies in a wafer-level fan-out package. In an example, an electronic device includes a wafer-level fan-out package. The wafer-level fan-out package includes a first integrated circuit (IC) die, a second IC die, and a redistribution structure. The first IC die includes a transmitter circuit. The second IC die includes a receiver circuit. The redistribution structure includes physical channels electrically connected to and between the transmitter circuit and the receiver circuit. The transmitter circuit is configured to transmit multiple single-ended data signals and a differential clock signal through the physical channels to the receiver circuit. The receiver circuit is configured to capture data from the multiple single-ended data signals using a first single-ended clock signal based on the differential clock signal.

Abstract: It has been established that CD55 expression on human mesenchymal stem cells (hMSCs) is positively correlated with successful allogenic transplantation procedures. Compositions and methods for improved hMSCs, having increased expression of CD55 mRNA and/or increased expression of CD55 on the surface of the cell as compared to a control cell, are provided. Methods include isolating hMSCs from a tissue that naturally has increased CD55 expression, such as adipose tissue derived hMSC (AT-hMSC); and/or in vitro culturing hMSCs in the presence of one or more active agents that stimulates or enhances the expression of CD55 mRNA, and/or increases the surface expression of CD55 in the hMSC to provide improved hMSCs. Preferred active agents include HMG-CoA reductase inhibitors such as atorvastatin and EGFR inhibitors such as erlotinib. Compositions and methods for administering the improved hMSCs to a subject in need thereof are also provided.

Abstract: A DAC-based transmit driver architecture with improved bandwidth and techniques for driving data using such an architecture. One example transmit driver circuit generally includes an output node and a plurality of digital-to-analog converter (DAC) slices. Each DAC slice has an output coupled to the output node of the transmit driver circuit and includes a bias transistor having a drain coupled to the output of the DAC slice and a multiplexer having a plurality of inputs and an output coupled to a source of the bias transistor.

Abstract: A multiplication injection locked oscillator (MIILO) circuitry includes a ring injection locked oscillator (ILO) circuitry that outputs clock signals, a first switching circuitry and a second switching circuitry. The ring ILO circuitry includes a first path having first delay stages, and a second path having a second delay stages. The first switching circuitry is connected to the first path and a voltage supply node. The first switching circuitry receives a first control signal and a second control signal and selectively connects the voltage supply node to the first path. The second switching circuitry is connected to the second path and a reference voltage node. The second switching circuitry receives the first control signal and the second control signal and selectively connects the reference voltage node to the second path.

Abstract: Clock generation circuitry includes quadrature locked loop circuitry having first injection locked oscillator circuitry, second injection locked oscillator circuitry, and XOR circuitry. The first injection locked oscillator circuitry receives a first input signal and a second input signal and outputs first clock signals. The first input signal and the second input signal correspond to a reference clock signal. The second injection locked oscillator circuitry is coupled to outputs of the first injection locked oscillator circuitry, and receives the first clock signals and generates second clock signals. The XOR circuitry receives the second clock signals and generates a first clock signal, a second clock signal, a third clock signal, and a fourth clock signal. The frequencies of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal are greater than the frequency of the reference clock signal.

Abstract: A laser leveling tool comprising: a laser source configured to emit a laser beam; and a digital laser beam projection system which transmits the laser beam emitted from the laser source and converts the laser beam into a projection pattern that is to be projected to a target surface; wherein the digital laser beam projection system comprises a pixel panel arranged to receive the laser beam emitted from the laser source and comprising pixel units which are selectively activated to reflect or transmit the laser beam, the reflected or transmitted laser beam conforming to a desired projection pattern to form a patterned laser beam.

Abstract: Provided are mesenchymal stromal cells as a reprogramming source for ipsc induction. In particular, Provided is a method for generating induced mesnchyaml stromal cells (iMSCs), the iMSC generated by the method as well as the use thereof.

Abstract: An N-channel interleaved Analog-to-Digital Converter (ADC) has a variable delay added to each ADC's input sampling clock. The variable delays are each programmed by a Successive-Approximation-Register (SAR) during calibration to minimize timing skews between channels. In each channel the ADC output is filtered, and a product derivative correlator generates a product derivative factor for correlation to two adjacent ADC channels. A matrix processor arranges the product derivative factors from the product derivative correlators into a matrix that is multiplied by a correlation matrix. The correlation matrix is a constant generated from an N×N shift matrix. The matrix processor outputs a sign-bit vector. Each bit in the sign-bit vector determines when tested SAR bits are set or cleared to adjust a channel's variable delay. Sampling clock and component timing skews are reduced to one LSB among all N channels.