Patents by Inventor Chi Fung

Chi Fung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230155599
    Abstract: An N-channel interleaved Analog-to-Digital Converter (ADC) has a variable delay added to each ADC's input sampling clock. The variable delays are each programmed by a Successive-Approximation-Register (SAR) during calibration to minimize timing skews between channels. Each channel receives a sampling clock with a different phase delay. The sampling clocks are overlapping multi-phase clocks rather than non-overlapping. Overlapping the multi-phase clocks allows the sampling pulse width to be enlarged, providing more time for the sampling switch to remain open and allow analog voltages to equalize through the sampling switch. Higher sampling-clock frequencies are possible than when non-overlapping clocks are used. The sampling clock is boosted in voltage by a bootstrap driver to increase the gate voltage on the sampling switch, reducing the ON resistance. Sampling clock and component timing skews are reduced to one LSB among all N channels.
    Type: Application
    Filed: January 21, 2022
    Publication date: May 18, 2023
    Inventor: Chi Fung LOK
  • Patent number: 11646747
    Abstract: An N-channel interleaved Analog-to-Digital Converter (ADC) has a variable delay added to each ADC's input sampling clock. The variable delays are each programmed by a Successive-Approximation-Register (SAR) during calibration to minimize timing skews between channels. Each channel receives a sampling clock with a different phase delay. The sampling clocks are overlapping multi-phase clocks rather than non-overlapping. Overlapping the multi-phase clocks allows the sampling pulse width to be enlarged, providing more time for the sampling switch to remain open and allow analog voltages to equalize through the sampling switch. Higher sampling-clock frequencies are possible than when non-overlapping clocks are used. The sampling clock is boosted in voltage by a bootstrap driver to increase the gate voltage on the sampling switch, reducing the ON resistance. Sampling clock and component timing skews are reduced to one LSB among all N channels.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: May 9, 2023
    Assignee: Caelus Technologies Limited
    Inventor: Chi Fung Lok
  • Patent number: 11641210
    Abstract: An N-channel interleaved Analog-to-Digital Converter (ADC) has a variable delay added to each ADC's input sampling clock. The variable delays are each programmed by a Successive-Approximation-Register (SAR) during calibration to minimize timing skews between channels. In each channel the ADC output is filtered, and a product derivative correlator generates a product derivative factor for correlation to two adjacent ADC channels. A matrix processor arranges the product derivative factors from the product derivative correlators into a matrix that is multiplied by a correlation matrix. The correlation matrix is a constant generated from an N×N shift matrix. The matrix processor outputs a sign-bit vector. Each bit in the sign-bit vector determines when tested SAR bits are set or cleared to adjust a channel's variable delay. Sampling clock and component timing skews are reduced to one LSB among all N channels.
    Type: Grant
    Filed: November 29, 2021
    Date of Patent: May 2, 2023
    Assignee: Caelus Technologies Limited
    Inventors: Chi Fung Lok, Zhi Jun Li
  • Patent number: 11632121
    Abstract: An N-channel interleaved Analog-to-Digital Converter (ADC) has a variable delay added to each ADC's input sampling clock. The variable delays are each programmed by a Successive-Approximation-Register (SAR) during calibration to minimize timing skews between channels. An auto-correlator generates a sign of a correlation error for a pair of ADC digital outputs. SAR bits are tested with the correlation sign bit determining when to add or subtract SAR bits. First all pairs are calibrated in a first level of a binary tree of mux-correlators. Then skews between remote pairs and groups are calibrated in upper levels of the binary tree using auto-correlators with inputs muxed from groups of ADC outputs input to the binary tree of mux-correlators. The binary tree of mux-correlators can include bypasses for odd and non-binary values of N. Sampling clock and component timing skews are reduced to one LSB among both adjacent channels and remote channels.
    Type: Grant
    Filed: November 18, 2021
    Date of Patent: April 18, 2023
    Assignee: Caelus Technologies Limited
    Inventors: Chi Fung Lok, Xiaoyong He, Zhi Jun Li
  • Patent number: 11625293
    Abstract: A fault model representation of a computer network is generated, wherein the computer network includes a set of connected computer network elements that was at least in part configured based on a specified declarative intent in forming the computer network. A symptom representation for the computer network is determined based on telemetry data of one or more elements of the set of connected computer network elements and a behavior specification repository identifying symptoms and their associated root causes. The fault model representation and the symptom representation are provided to a root cause analysis to determine one or more root causes of one or more detected symptoms of the computer network.
    Type: Grant
    Filed: August 9, 2021
    Date of Patent: April 11, 2023
    Assignee: Apstra, Inc.
    Inventors: Aleksandar Luka Ratkovic, Chi Fung Michael Chan
  • Publication number: 20230045402
    Abstract: A laser leveling device includes at least one laser emitting device for emitting a laser marking, in particular a one-dimensional laser marking, in an emission direction onto a projection surface. The laser emitting device includes a first sensor device for ascertaining the actual alignment of the at least one laser emitting device with respect to the projection surface, a controller which is designed to calculate a target alignment of the at least one laser emitting device at least on the basis of the ascertained actual alignment of the at least one laser emitting device with respect to the projection surface, and a positioning device for aligning the at least one laser emitting device according to the target alignment. The disclosure additionally relates to a leveling method.
    Type: Application
    Filed: November 26, 2020
    Publication date: February 9, 2023
    Inventors: Martin Pohlmann, Wah Pong Calvin Chan, Axel Rumberg, Philip Cheung, Eddie Kwan, Chi Fung Chan
  • Patent number: 11567994
    Abstract: A method for configuring a computing infrastructure is disclosed. The method comprises representing at least a portion of the computing infrastructure as a graph representation of computing infrastructure elements including a computing infrastructure node and a computing infrastructure edge, detecting a change in the graph representation of computing infrastructure elements, and determining whether the change affects a graph representation query pattern. In the event the change affects the graph representation query pattern, the change is notified to a query agent associated with the graph representation query pattern.
    Type: Grant
    Filed: August 1, 2017
    Date of Patent: January 31, 2023
    Assignee: Apstra, Inc.
    Inventors: Mansour Jad Karam, Aleksandar Luka Ratkovic, Raghavendra Rachamadugu, Chi Fung Michael Chan, Eitan Joffe, Maksim Kulkin
  • Patent number: 11554138
    Abstract: The present disclosure relates to methods of using cisplatin active agents in which reduced organ toxicity is observed are provided. In the subject methods, an effective amount is administrated to the host before administration of an effective amount of cisplatin active agents. The cisplatin toxicity reducing agent comprising of stable bismuth(III) complexes or pharmaceutically acceptable salts reduces the levels of undesired toxicity of cisplatin active agents without compromising their anticancer activity. Also provided are methods for use in practicing the subject methods in the treatment of different disease conditions.
    Type: Grant
    Filed: July 14, 2016
    Date of Patent: January 17, 2023
    Assignee: THE UNIVERSITY OF HONG KONG
    Inventors: Hongzhe Sun, Chi-Fung Godfrey Chan, Shing Chan, Runming Wang
  • Publication number: 20220224608
    Abstract: A first device verification model is sent to a first agent on a first device providing at least a portion of the service. The first agent is able to monitor based on the first device verification model a parameter of the first device related to the service. A second device verification model is sent to a second agent on a second device providing at least a portion of the service, wherein the second agent is able to monitor based on the second device verification model a parameter of the second device related to the service. A report is received from the first agent of at least the parameter of the first device. A report is received from the second agent of at least the parameter of the second device. At least the parameter of the first device and at least the parameter of the second device are analyzed to determine whether the service is functioning as intended.
    Type: Application
    Filed: March 31, 2022
    Publication date: July 14, 2022
    Inventors: Mansour Jad Karam, Aleksandar Luka Ratkovic, Chi Fung Michael Chan
  • Patent number: 11323338
    Abstract: A first device verification model is sent to a first agent on a first device providing at least a portion of the service. The first agent is able to monitor based on the first device verification model a parameter of the first device related to the service. A second device verification model is sent to a second agent on a second device providing at least a portion of the service, wherein the second agent is able to monitor based on the second device verification model a parameter of the second device related to the service. A report is received from the first agent of at least the parameter of the first device. A report is received from the second agent of at least the parameter of the second device. At least the parameter of the first device and at least the parameter of the second device are analyzed to determine whether the service is functioning as intended.
    Type: Grant
    Filed: April 11, 2019
    Date of Patent: May 3, 2022
    Assignee: Apstra, Inc.
    Inventors: Mansour Jad Karam, Aleksandar Luka Ratkovic, Chi Fung Michael Chan
  • Publication number: 20220102293
    Abstract: Examples described herein generally relate to communication between integrated circuit (IC) dies in a wafer-level fan-out package. In an example, an electronic device includes a wafer-level fan-out package. The wafer-level fan-out package includes a first integrated circuit (IC) die, a second IC die, and a redistribution structure. The first IC die includes a transmitter circuit. The second IC die includes a receiver circuit. The redistribution structure includes physical channels electrically connected to and between the transmitter circuit and the receiver circuit. The transmitter circuit is configured to transmit multiple single-ended data signals and a differential clock signal through the physical channels to the receiver circuit. The receiver circuit is configured to capture data from the multiple single-ended data signals using a first single-ended clock signal based on the differential clock signal.
    Type: Application
    Filed: September 29, 2020
    Publication date: March 31, 2022
    Inventors: Chi Fung POON, Asma LARABA, Parag UPADHYAYA
  • Publication number: 20210353621
    Abstract: The present application relates to treating and/or preventing prostate cancer, including metastatic and/or castrate-resistant prostate cancer, in a subject in need of treatment, comprising administering a compound of Formula (I), or a pharmaceutically acceptable salt, enantiomer, stereoisomer, solvate, polymorph, isotopic derivative, or prodrug thereof, wherein R1, R2, R3, X1, X2, X3, X4, and n are defined herein.
    Type: Application
    Filed: May 11, 2021
    Publication date: November 18, 2021
    Inventors: Ronald PECK, Yongqing HUANG, Chi Fung KEUNG
  • Publication number: 20210341287
    Abstract: A laser leveling tool comprising: gesture control means comprises at least one sensor adapted to sense gestures and/or movements of a user; and a controller in communication with the gesture control means for receiving signals from the sensor and generating control commands for the tool based on the received signals, the control commands comprising at least ON/OFF states of laser beam patterns that the tool can project.
    Type: Application
    Filed: September 12, 2018
    Publication date: November 4, 2021
    Inventors: Chi Fung Chan, Yuk Wah Siu, Wah Pong Calvin Chan, Kenneth Yuen, Chun Pong David Chan
  • Patent number: 11165461
    Abstract: A system for wireless communication may include a passive gain front end circuit coupled to an N-path filter. In a transmit mode, signals may be provided to an antenna through the passive gain circuit. In the transmit mode, the N-path filter may provide isolation at the antenna. In a receive mode, the passive gain front end may provide gain to the received signal. In the receive mode, the N-path filter may be used to downconvert the received signal.
    Type: Grant
    Filed: January 16, 2020
    Date of Patent: November 2, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Chi-Fung Kwok, Vasileios Mylonakis, Idris El-Fatmaoui
  • Publication number: 20210325184
    Abstract: A laser leveling tool comprising: a laser source configured to emit a laser beam; and a digital laser beam projection system which transmits the laser beam emitted from the laser source and converts the laser beam into a projection pattern that is to be projected to a target surface; wherein the digital laser beam projection system comprises a pixel panel arranged to receive the laser beam emitted from the laser source and comprising pixel units which are selectively activated to reflect or transmit the laser beam, the reflected or transmitted laser beam conforming to a desired projection pattern to form a patterned laser beam.
    Type: Application
    Filed: September 12, 2018
    Publication date: October 21, 2021
    Inventors: Chi Fung Chan, Hopong Cheung, Yuenyu Wong, Ben-Hur Seneca
  • Patent number: 11146282
    Abstract: A first calibration measures capacitor array mis-match and updates a Look-Up Table (LUT) with calibrated weights that are copied to both a positive LUT and a negative LUT, and then adjusted for non-linearity errors by a second calibration using a Least Mean-Square (LMS) method. The binary code in the Successive-Approximation Register (SAR) is complemented to generate a complement code with a sign bit. When the sign bit is positive, entries for complement code bits=1 are read from the positive LUT and summed, a first offset added, and the sum normalized to get a corrected code. When the sign bit is negative, entries for complement code bits=0 are read from the negative LUT and summed, a second offset added, and the sum normalized to get the corrected code. A Multi-Variable Stochastic Gradient Descent method generates polynomial coefficients that further correct the corrected code.
    Type: Grant
    Filed: January 4, 2021
    Date of Patent: October 12, 2021
    Assignee: Caelus Technologies Limited
    Inventors: Chi Fung Lok, Xiaoyong He, Zhi Jun Li
  • Patent number: 11086709
    Abstract: A fault model representation of a computer network is generated, wherein the computer network includes a set of connected computer network elements that was at least in part configured based on a specified declarative intent in forming the computer network. A symptom representation for the computer network is determined based on telemetry data of one or more elements of the set of connected computer network elements and a behavior specification repository identifying symptoms and their associated root causes. The fault model representation and the symptom representation are provided to a root cause analysis to determine one or more root causes of one or more detected symptoms of the computer network.
    Type: Grant
    Filed: May 1, 2019
    Date of Patent: August 10, 2021
    Assignee: Apstra, Inc.
    Inventors: Aleksandar Luka Ratkovic, Chi Fung Michael Chan
  • Patent number: 11003203
    Abstract: A circuit arrangement for calibrating a circuit in an integrated circuit device is described. The circuit arrangement may comprise a main circuit configured to receive input data at a first input and generate output data at a first output, wherein the output data is based upon the input data and a function of the main circuit; a replica circuit configured to receive calibration data at a second input and generate calibration output data, based upon the calibration data, at a second output, wherein the replica circuit provides a replica function of the function of the main circuit; and a calibration circuit configured to receive the output data from the main circuit during a foreground calibration mode, and the calibration output data from the replica circuit during a background calibration mode; wherein the calibration circuit provides control signals to the main circuit during the background calibration mode. A method of calibrating a circuit in an integrated circuit device is also described.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: May 11, 2021
    Assignee: XILINX, INC.
    Inventors: Chi Fung Poon, Asma Laraba, Parag Upadhyaya
  • Patent number: 10964777
    Abstract: Integrated circuits such as multi-channel receivers may require loop inductors resistant to electromagnetic field interference. Such loop inductors may include multiple non-overlapping loops each defining a corresponding dipole, the multiple dipoles summing to zero, with at least one of said loops having unequal areas. The multiple non-overlapping loops may include: a center loop defining a central magnetic dipole; and a plurality of peripheral loops equally spaced around a perimeter of the center loop, each peripheral loop defining a peripheral magnetic dipole oriented opposite the central magnetic dipole, the plurality of peripheral loops substantially canceling a field from the central magnetic dipole. The total number of loops may be odd, with particular embodiments of three, five, and seven loop designs disclosed. Single and multi-turn embodiments are provided.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: March 30, 2021
    Assignee: Credo Technology Group Ltd.
    Inventors: Xike Liu, Kuan Peng, Chan Ho Yeung, Yifei Dai, Lawrence Chi Fung Cheng, Runsheng He
  • Patent number: 10944584
    Abstract: Mass-manufactured cables suitable for large communication centers may convert from differential PAM4 interface signaling to parallel single-ended NRZ transit signaling at 53.125 GBd to provide bidirectional data rates up to 800 Gbps and beyond. One illustrative cable embodiment includes: electrical conductors connected between a first connector and a second connector, each adapted to fit into an Ethernet port of a corresponding host device to receive an electrical input signal to the cable conveying an outbound data stream from the host device and to provide an electrical output signal from the cable conveying an inbound data stream to that host device. The electrical input and output signals employ differential PAM4 modulation to convey the inbound and outbound data streams.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: March 9, 2021
    Assignee: CREDO TECHNOLOGY GROUP LIMITED
    Inventors: Lawrence Chi Fung Cheng, Rajan Pai