Abstract: The present disclosure, in some embodiments, relates to an integrated chip structure. The integrated chip structure includes a first via disposed on a first side of a substrate. A second via is disposed on the first side of the substrate and is laterally separated from the first via. An interconnect wire vertically contacts the second via. A through-substrate via (TSV) extends through the substrate to physically contact one or more of the second via and the interconnect wire. The first via has a first width and the second via has a second width. The second width is between approximately 2,000% and approximately 5,000% larger than the first width.

Abstract: A target droplet source for an extreme ultraviolet (EUV) source includes a droplet generator configured to generate target droplets of a given material. The droplet generator includes a nozzle configured to supply the target droplets in a space enclosed by a chamber. The target droplet source further includes a sleeve disposed in the chamber distal to the nozzle. The sleeve is configured to provide a path for the target droplets in the chamber.

Abstract: Methods for isolating two adjacent transistors are disclosed. A substrate has a first semiconducting fin on a first region and a second semiconducting fin on a second region, and the first semiconducting fin and the second semiconducting fin contact each other at a jog region. A dummy gate within or adjacent the jog region is removed to expose a portion of the first semiconducting fin and form an isolation volume. Etching is performed to remove the exposed portion of the first semiconducting fin and create a trench in the substrate. The trench and the isolation volume are filled with at least one dielectric material to form an electrically isolating structure between the first region and the second region. Additional dummy gates in each region can be removed and replaced with an electrically conductive material to form two adjacent transistors electrically isolated from each other.

Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a first capacitor conductor disposed over an isolation structure arranged within a substrate. The isolation structure laterally extends past opposing outer sidewalls of the first capacitor conductor. A capacitor dielectric is arranged along one of the opposing outer sidewalls of the first capacitor conductor and over a top surface of the first capacitor conductor. A second capacitor conductor is arranged along an outer sidewall of the capacitor dielectric and over a top surface of the capacitor dielectric. The second capacitor conductor laterally overlaps parts of both the capacitor dielectric and the first capacitor conductor.

Abstract: A semiconductor device package includes a number of interposers mounted to the carrier, wherein the number of interposers may be arranged in an irregular pattern.

Abstract: A semiconductor structure and a method for forming a semiconductor structure are provided. The semiconductor structure includes: a substrate; a doped region within the substrate; a pair of source/drain regions extending along a first direction on opposite sides of the doped region; a gate electrode disposed in the doped region, wherein the gate electrode has a plurality of first segments between the pair of source/drain regions; and a protection structure overlapping the gate electrode.

Abstract: A UE activates a timer for applying access control to transmissions associated with a certain access category during an access control period, in response to a first system information message received via a radio interface and a mobile-originated access request (1702). While the timer is running, the UE receives a second message that indicates a potential transition of the UE (i) from a current state associated with a protocol for controlling radio resources to another state associated with the protocol, or (ii) from a current cell to a new cell (1704). In response to the second message, the UE continues to apply the access control to the transmissions for the access category, for a remainder of the access control period (1706).

Abstract: A multiple die container load port may include a housing with an opening, and an elevator to accommodate a plurality of different sized die containers. The multiple die container load port may include a stage supported by the housing and moveable within the opening of the housing by the elevator. The stage may include one or more positioning mechanisms to facilitate positioning of the plurality of different sized die containers on the stage, and may include different portions movable by the elevator to accommodate the plurality of different sized die containers. The multiple die container load port may include a position sensor to identify one of the plurality of different sized die containers positioned on the stage.

Abstract: A method of producing a container product comprises providing a mold including a first part and a second part. The mold is closed to define a cavity having a first area and a second area. A molten plastic composition including a polymer and a physical blowing agent is filled into the cavity. Then, the molten plastic composition in the cavity is cooled, such that the molten plastic composition in the first area is completely cooled and solidifies or a central portion of the first area has micro uncooled molten plastic composition. The second area has the plastic composition in the molten state. The first part of the mold is moved in the axial direction. The molten plastic composition in the second area forms a beehive foam after foaming and expansion. Then, the foamed container product in the mold is cooled to take shape and then removed after opening the mold.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate including a base and a fin structure over the base. The fin structure includes a nanostructure. The semiconductor device structure includes a gate stack over the base and wrapped around the nanostructure. The gate stack has an upper portion and a sidewall portion, the upper portion is over the nanostructure, and the sidewall portion is over a first sidewall of the nanostructure. The semiconductor device structure includes a first inner spacer and a second inner spacer over opposite sides of the sidewall portion. A sum of a first width of the first inner spacer and a second width of the second inner spacer is greater than a third width of the sidewall portion as measured along a longitudinal axis of the fin structure.

Abstract: A package includes a sensor die, and an encapsulating material encapsulating the sensor die therein. A top surface of the encapsulating material is substantially coplanar with or higher than a top surface of the sensor die. A plurality of sensing electrodes is higher than the sensor die and the encapsulating material. The plurality of sensing electrodes is arranged as a plurality of rows and columns, and the plurality of sensing electrodes is electrically coupled to the sensor die. A dielectric layer covers the plurality of sensing electrodes.

Abstract: Optical devices and methods of manufacture are presented in which a mirror structure is utilized to transmit and receive optical signals to and from an optical device. In embodiments the mirror structure receives optical signals from outside of an optical device and directs the optical signals through at least one mirror to an optical component of the optical device.

Abstract: A redistribution structure is made using filler-free insulating materials with high shrinkage rate. As a result, good planarity may be achieved without the need to perform a planarization of each insulating layer of the redistribution structure, thereby simplifying the formation of the redistribution structure.

Abstract: A semiconductor structure and a manufacturing method therefor are disclosed. The semiconductor structure includes an interposer, where the interposer includes a deep trench capacitor array and an isolation structure. The deep trench capacitor array includes multiple deep trench capacitors, and the isolation structure at least partially surrounds a deep trench capacitor on the outmost edge side of the deep trench capacitor array.

Abstract: A method for manufacturing an electronic device is provided. The method includes providing a first substrate. The method further includes forming a bank layer on the first substrate. The bank layer includes a bank wall and a first opening, and the first opening adjacent to the bank wall. The method further includes forming a light conversion layer in the first opening. The method further includes forming a spacer on the bank wall. The method further includes providing a second substrate. The method further includes transferring a plurality of electronic units to the second substrate. The method further includes overlapping the first substrate and second substrate, so that the spacer is located between the first substrate and the second substrate.

Abstract: In a method for inspecting pattern defects, a plurality of patterns are formed over an underlying layer. The plurality of patterns are electrically isolated from each other. A part of the plurality of patterns are scanned with an electron beam to charge the plurality of patterns. An intensity of secondary electrons emitted from the scanned part of the plurality of patterns is obtained. One or more of the plurality of patterns that show an intensity of the secondary electrons different from others of the plurality of patterns are searched.

Abstract: A physical vapor deposition (PVD) target for performing a PVD process is provided. The PVD target includes a backing plate and a target plate coupled to the backing plate. The target plate includes a sputtering source material and a dopant, with the proviso that the dopant is not impurities in the sputtering source material. The sputtering source material includes a diffusion barrier material.

Abstract: A spatial light modulator device includes an array of spatial light modulator cells located over a substrate. Each of the spatial light modulator cells includes: a layer stack including a phase change material plate, a spacer dielectric material plate that underlies the phase change material plate, and a metallic heater plate underlying the spacer dielectric material plate and including outer sidewalls; and a pair of bottom electrode via structures contacting a respective surface segment of a bottom surface of the metallic heater plate. Each of the outer sidewalls of the metallic heater plate is vertically coincident with a respective sidewall of the spacer dielectric material plate and with a respective sidewall of the phase change material plate.

Abstract: The present disclosure relates to an integrated circuit (IC) that includes a boundary region defined between a low voltage region and a high voltage region, and a method of formation. In some embodiments, the integrated circuit comprises an isolation structure disposed in the boundary region of the substrate. A first polysilicon component is disposed directly on an upper surface of the substrate alongside the isolation structure. A boundary dielectric layer is disposed on the isolation structure. A second polysilicon component is disposed on the sacrifice dielectric layer.

Abstract: The present invention discloses an electromagnetic air pump including an air chamber operable to be compressed or expanded. The air chamber is defined by a platform surface and a rubber cap operable to be pressed downward. The rubber cap includes a support and a cover. During the operation of the electromagnetic air pump, the cover is configured to bear against the support with the platform surface when the cover is pressed downward. When the air chamber is compressed or expanded, each pair of geometrically symmetrical parts of the cover corresponds to a pair of displacement changes relative to the platform surface, wherein a difference between the pair of displacement changes is not greater than 5%. Thus, the rubber cap is provided with an effect of a substantially uniform stress.