Abstract: A method of manufacturing an electronic device is provided. The method includes providing a substrate, disposing a composite conductive layer on the substrate, and patterning the composite conductive layer into a composite conductive pattern in two wet etching steps. Moreover, the two wet etching steps use different etching solutions.

Abstract: A Bluetooth connection system is provided. The Bluetooth connection system includes a control host and a Bluetooth audio device. The control host includes a transmission unit. The Bluetooth audio device wirelessly communicates with the transmission unit, wherein the control host receives an instruction, then turns on the transmission unit and executes a search task to find the Bluetooth audio device around the control host. When the Bluetooth audio device does not return a confirmation Bluetooth connection signal to the control host, the control host sends a wake-up signal to the Bluetooth audio device to start a re-pairing procedure.

Abstract: A semiconductor device includes a FEOL structure and a BEOL structure. The BEOL structure is formed over the FEOL structure and includes a conductive layer, an etching stop layer (ESL) structure, a through via and a barrier layer. The ESL structure is formed over the conductive layer and has a first recess and a lateral surface. The through via passes through the ESL structure to form the first recess and the lateral surface. The barrier layer covers the lateral surface and the first recess. The first recess is recessed with respect to the lateral surface, and the first recess has a first depth ranging between 1 nm and 7 nm.

Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a transistor region and an one time programmable (OTP) capacitor region, forming a first fin-shaped structure on the transistor region and a second fin-shaped structure on the OTP capacitor region, and then performing an oxidation process to form a gate oxide layer on the first fin-shaped structure and the second fin-shaped structure. Preferably, the first fin-shaped structure and the second fin-shaped structure have different shapes under a cross-section perspective.

Abstract: A projection device and an auto-focus method of the projection device are provided. A projection distance between a projection lens of the projection device and a projection surface is detected to generate a distance detection signal. A control unit updates an expanded look-up table based on the original look-up table, the distance detection signal, an optimal motor step, and an adjustment completion time, where the optimal motor step and the adjustment completion time are obtained through a manual focus operation. An auto-focus operation is performed based on the distance detection signal and the updated expanded look-up table.

Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.

Abstract: An integrated circuit design implementation system includes a synthesis tool configured to: receive a behavioral description of each of a plurality of first components; generate first netlists based on the behavioral descriptions of the first components; receive connection information of a plurality of second components, wherein the connection information comprises physical arrangement and connectivity among the first components and the second components; generate a plurality of third components, wherein each of the third components operatively corresponds to an interface between a pair of one of the first components and one of the second components; and transform the first netlists to a second netlist based on first vertices, second vertices, third vertices, and edges. The first vertices correspond to the first components, respectively, the second vertices correspond to the second components, respectively, and the third vertices correspond to the third components, respectively.

Abstract: Equipment adapted for a waste volume expansion stabilization process has an autoclave and a waste carrying container. The waste carrying container is configured for carrying a pile of waste, is positioned in the autoclave, and has a chamber and a steam conducting unit installed in the chamber and having multiple steam tubes. Each steam tube connects with the autoclave via a first opening thereof and connects with the chamber via a second opening thereof. High pressure steam flows into the steam tubes from the first openings and flows into the chamber to be mixed with the pile of the waste via the second opening. Surface contact areas between the steam and the pile of waste is increased. The performance of the waste volume expansion stabilization process is improved and processing time for the waste volume expansion stabilization process can be reduced.

Abstract: Provided is a semiconductor device including: a substrate, a plurality of isolation structures, a plurality of channel layers, and a gate structure. The substrate includes a plurality of fins thereon. The plurality of isolation structures are respectively disposed between the plurality of fins. A top surface of the plurality of isolation structures is higher than a top surface of the plurality of fins to form a plurality of openings. The plurality of channel layers are respectively disposed in the plurality of openings. Each channel layer is in contact with a corresponding fin and extends to cover a lower sidewall of a corresponding isolation structure, thereby forming a U-shaped structure. The gate structure is filled in the plurality of openings and extends to cover the top surface of the plurality of isolation structures.

Abstract: A method of manufacturing a semiconductor device includes forming a fin structure over a substrate, forming a sacrificial gate structure over the fin structure, and etching a source/drain (S/D) region of the fin structure to form an S/D recess. The fin structure includes first semiconductor layers and second semiconductor layers alternately stacked. The method further includes depositing an insulating dielectric layer in the S/D recess, depositing an etch protection layer over a bottom portion of the insulating dielectric layer, and partially removing the insulating dielectric layer. The method further includes growing an epitaxial S/D feature in the S/D recess. The bottom portion of the insulating dielectric layer interposes the epitaxial S/D feature and the substrate.

Abstract: A UE communicating in DC with an MN and an SN detects a master cell group (MCG) failure associated with the MN. In response to detecting the MCG failure, the UE performs an MCG recovery procedure by transmitting an MCG failure information message to the SN, receiving an MCG failure recovery message from the SN, and transmitting an MCG failure recovery complete message to the MN.

Abstract: A device for removing particles in a gas stream includes a first cylindrical portion configured to receive the gas stream containing a target gas and the particles, a rotatable device disposed within the first cylindrical portion and configured to generate a centrifugal force when in a rotational action to divert the particles away from the rotatable device, a second cylindrical portion coupled to the first cylindrical portion and configured to receive the target gas, and a third cylindrical portion coupled to the first cylindrical portion and surrounding the second cylindrical portion, the third cylindrical portion being configured to receive the diverted particles.

Abstract: A method of fabricating a contact structure includes the following steps. An opening is formed in a dielectric layer. A conductive material layer is formed within the opening and on the dielectric layer, wherein the conductive material layer includes a bottom section having a first thickness and a top section having a second thickness, the second thickness is greater than the first thickness. A first treatment is performed on the conductive material layer to form a first oxide layer on the bottom section and on the top section of the conductive material layer. A second treatment is performed to remove at least portions of the first oxide layer and at least portions of the conductive material layer, wherein after performing the second treatment, the bottom section and the top section of the conductive material layer have substantially equal thickness.

Abstract: A drug carrier with a property of crossing the blood-brain barrier comprises an extracellular vesicle with a human leukocyte antigen-G antibody on its surface. This carrier can serve as a pharmaceutical composition for promoting apoptosis of brain tumor cells, inhibiting growth of brain tumor cells, or reducing expression of O6-methylguanine-DNA methyltransferase (MGMT) in brain tumor cells. These effects contribute to the treatment of glioblastoma multiforme (GBM).

Abstract: An electronic device is provided. The electronic device includes a display panel and a controller coupled to the display panel. The display panel is configured to update displayed images at a refresh rate. The controller is configured to receive a target frame rate from a first application. The controller is further configured to determine a frame rate according to the refresh rate and the target frame rate. The frame rate is a factor of the refresh rate. The controller is further configured to control the first application to draw images at the frame rate.

Abstract: A control device includes multi-stage control circuits. An i-th stage control circuit includes an input signal generator and an acknowledge signal generator. The input signal generator generates an i+1-th stage input signal according to a first inverted output signal and an i+1-th stage acknowledge signal. The acknowledge signal generator generates an i-th stage acknowledge signal according to an i-th stage delayed input signal and a second inverted output signal, wherein i is an integer larger than 1. Phases of the first inverted output signal and the second inverted output signal are opposite to a phase of an i-th stage output signal generated by an i-th stage pulse signal generator.

Abstract: An integrated circuit includes a plurality of routing lines extending along a first direction, the plurality of routing lines being separated in the first direction by integral multiples of a nominal minimum pitch. The integrated circuit includes a plurality of standard cells, at least one of the plurality of standard cells having a first boundary coinciding with a routing line of the plurality of routing lines, and a second boundary offset from each of the plurality of routing lines.

Abstract: A composite tray includes a tray body and an external supporting member. The tray body includes a loading plate and a plurality of side walls. The side walls protrude from the loading plate. The side walls and the loading plate jointly form an accommodating groove, and the accommodating groove has an opening. The external supporting member includes a supporting plate and a plurality of assembly members. The supporting plate is located in the accommodating groove and divides the accommodating groove into an inner space and an outer space. The inner space is located between the supporting plate and the loading plate. The outer space is located between the opening and the supporting plate. The assembly members are connected around the supporting plate and respectively assembled to the side walls, and a thickness of the supporting plate is less than a thickness of the loading plate.

Abstract: In a method of manufacturing a semiconductor device, sacrificial patterns are formed over a hard mask layer disposed over a substrate, sidewall patterns are formed on sidewalls of the sacrificial patterns, the sacrificial patterns are removed, thereby leaving the sidewall patterns as first hard mask patterns, the hard mask layer is patterned by using the first hard mask patters as an etching mask, thereby forming second hard mask patterns, and the substrate is patterned by using the second hard mask patterns as an etching mask, thereby forming fin structures. Each of the first sacrificial patterns has a tapered shape having a top smaller than a bottom.

Abstract: A polysilicon well is formed at a cross-road portion between a plurality of pixel sensors in a pixel sensor array. Moreover, the underlying oxide layer between the polysilicon well and a semiconductor layer of the pixel sensor array may be thinner than other areas of the oxide layer. The polysilicon well and the thinner oxide layer may reduce the likelihood of and/or the magnitude of lateral etching that occurs during etching of the semiconductor layer to form recesses in which a BDTI structure of the pixel sensor array is formed. Moreover, the bottom of the BDTI structure being surrounded by the polysilicon well enables a voltage bias to be applied to the BDTI structure through the polysilicon well to passivate damage that might have occurred to the semiconductor layer around the bottom of the BDTI structure.