Patents by Inventor Chih-An Chen

Chih-An Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250120103
    Abstract: A method of forming a semiconductor device is disclosed. The method includes forming a plurality of isolation regions on a semiconductor substrate, forming a protective layer in a resistor region of the semiconductor substrate, after forming the protective layer, etching a gate dielectric layer to form first and second gate dielectric layers of a transistor in a transistor region of the semiconductor substrate, removing the protective layer, forming first and second dummy gate stacks over the first and second gate dielectric layers, respectively, forming a resistor in the resistor region, forming third and fourth dummy gate stacks over the resistor, and replacing each of the first, second, third, and fourth dummy gate stacks with a conductive material.
    Type: Application
    Filed: December 9, 2024
    Publication date: April 10, 2025
    Inventors: Liang-Hsiang Chen, Chinyu Su, Che-Chih Hsu
  • Publication number: 20250118612
    Abstract: A semiconductor package includes a photonic integrated circuit (PIC) die having a photonic layer, and an electronic integrated circuit (EIC) die bonded to the PIC die. The EIC die includes an optical region that allows the transmission of optical signals through the optical region towards the photonic layer, and a peripheral region outside of the optical region. The optical region includes optical concave/convex structures, a protection film and optically transparent material layers. The optical concave/convex structures are formed in the semiconductor structure. The protection film is conformally disposed over the optical concave/convex structures. The optically transparent material layers are disposed over the protection film and filling up the optical region. The peripheral region includes first bonding pads bonded to the photonic integrated circuit die, and via structures connected to the first bonding pads, wherein the protection film is laterally surrounding sidewalls of the via structures.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 10, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen Chen, Yu-Hung Lin, Chih-Hao Yu, Wei-Ming Wang, Chia-Hui Lin, Shih-Peng Tai
  • Publication number: 20250120153
    Abstract: In some embodiments, an integrated chip is provided. The integrated chip includes a source region and a drain region disposed in a substrate. A gate is disposed over the substrate and between the source region and the drain region. A silicide structure is disposed over the drain region. A first silicide blocking segment and a second silicide blocking segment are disposed directly over the drain region. The silicide structure continuously extends over the drain region from a first sidewall contacting the first silicide blocking segment to a second sidewall contacting the second silicide blocking segment, in a cross-sectional view.
    Type: Application
    Filed: December 18, 2024
    Publication date: April 10, 2025
    Inventors: Kong-Beng Thei, Chien-Chih Chou, Hsiao-Chin Tuan, Yi-Huan Chen, Alexander Kalnitsky
  • Publication number: 20250119654
    Abstract: This disclosure provides systems, methods, and devices for image processing that support enhanced white balancing operations. In a first aspect, a method of image processing includes receiving first image data obtained at a first aperture; determining a first output image frame based on the first image data by applying a first white balancing to at least a portion of the first image data; receiving second image data obtained at a second aperture; and determining a second output image frame based on the second image data by applying a second white balancing based on the first aperture and the second aperture to at least a portion of the second image data. The second white balancing may be based on a first compensation factor based on the first aperture and the second aperture used to adjust the first white balancing. Other aspects and features are also claimed and described.
    Type: Application
    Filed: March 25, 2022
    Publication date: April 10, 2025
    Inventors: Yi-Chun Hsu, Tai-Hsiang Jen, Zhi Qin, Tsung-yen Chen, Wei-Chih Liu
  • Patent number: 12273389
    Abstract: A method, computer system, and a computer program product for smart SDN is provided. The present invention may include recording and clustering a pod's behavior to generate a behavior transition model for the pod. The present invention may include watching a behavior of the pod and comparing the behavior to the generated behavior transition model. The present invention may include triggering a network policy change based on determining that the behavior of the pod is a misbehavior.
    Type: Grant
    Filed: March 22, 2022
    Date of Patent: April 8, 2025
    Assignee: International Business Machines Corporation
    Inventors: Jeff Hsueh-Chang Kuo, June-Ray Lin, Ying-Chen Yu, Chih-Wen Su
  • Patent number: 12274087
    Abstract: A field effect transistor includes a substrate having a transistor forming region thereon; an insulating layer on the substrate; a first graphene layer on the insulating layer within the transistor forming region; an etch stop layer on the first graphene layer within the transistor forming region; a first inter-layer dielectric layer on the etch stop layer; a gate trench recessed into the first inter-layer dielectric layer and the etch stop layer within the transistor forming region; a second graphene layer on interior surface of the gate trench; a gate dielectric layer on the second graphene layer and on the first inter-layer dielectric layer; and a gate electrode on the gate dielectric layer within the gate trench.
    Type: Grant
    Filed: November 21, 2022
    Date of Patent: April 8, 2025
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Chih Lai, Shih-Min Chou, Nien-Ting Ho, Wei-Ming Hsiao, Li-Han Chen, Szu-Yao Yu, Chung-Yi Chiu
  • Patent number: 12274070
    Abstract: A memory device and a manufacturing method thereof is described. The memory device includes a transistor structure over a substrate and a ferroelectric capacitor structure electrically connected with the transistor structure. The ferroelectric capacitor structure includes a top electrode layer, a bottom electrode layer and a ferroelectric stack sandwiched there-between. The ferroelectric stack includes a first ferroelectric layer, a first stabilizing layer, and one of a second ferroelectric layer or a second stabilizing layer. Materials of the first stabilizing layer and a second stabilizing layer include a metal oxide material.
    Type: Grant
    Filed: July 4, 2022
    Date of Patent: April 8, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Ting Lin, Wei-Chih Wen, Kai-Wen Cheng, Wu-Wei Tsai, Yu-Ming Hsiang, Yan-Yi Chen, Hai-Ching Chen, Yu-Ming Lin, Chung-Te Lin
  • Patent number: 12271113
    Abstract: Method of manufacturing semiconductor device includes forming photoresist layer over substrate. Forming photoresist layer includes combining first precursor and second precursor in vapor state to form photoresist material, wherein first precursor is organometallic having formula: MaRbXc, where M at least one of Sn, Bi, Sb, In, Te, Ti, Zr, Hf, V, Co, Mo, W, Al, Ga, Si, Ge, P, As, Y, La, Ce, Lu; R is substituted or unsubstituted alkyl, alkenyl, carboxylate group; X is halide or sulfonate group; and 1?a?2, b?1, c?1, and b+c?5. Second precursor is at least one of an amine, a borane, a phosphine. Forming photoresist layer includes depositing photoresist material over the substrate. The photoresist layer is selectively exposed to actinic radiation to form latent pattern, and the latent pattern is developed by applying developer to selectively exposed photoresist layer to form pattern.
    Type: Grant
    Filed: January 15, 2021
    Date of Patent: April 8, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chih-Cheng Liu, Yi-Chen Kuo, Jia-Lin Wei, Ming-Hui Weng, Yen-Yu Chen, Jr-Hung Li, Yahru Cheng, Chi-Ming Yang, Tze-Liang Lee, Ching-Yu Chang
  • Patent number: 12272554
    Abstract: A method of manufacturing semiconductor device includes forming a multilayer photoresist structure including a metal-containing photoresist over a substrate. The multilayer photoresist structure includes two or more metal-containing photoresist layers having different physical parameters. The metal-containing photoresist is a reaction product of a first precursor and a second precursor, and each layer of the multilayer photoresist structure is formed using different photoresist layer formation parameters. The different photoresist layer formation parameters are one or more selected from the group consisting of the first precursor, an amount of the first precursor, the second precursor, an amount of the second precursor, a length of time each photoresist layer formation operation, and heating conditions of the photoresist layers.
    Type: Grant
    Filed: July 27, 2023
    Date of Patent: April 8, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jia-Lin Wei, Ming-Hui Weng, Chih-Cheng Liu, Yi-Chen Kuo, Yen-Yu Chen, Yahru Cheng, Jr-Hung Li, Ching-Yu Chang, Tze-Liang Lee, Chi-Ming Yang
  • Publication number: 20250108430
    Abstract: An installation tool for a self-tapping rivet fastener contains: a body, a movable sleeve, a handle, a single-direction thrust bearing, a switcher, a drive rod, a transmission shaft, a cap, a locking element, and a screw nut. The body includes multiple ribs, two protrusions, two slots, a circular orifice, a stepped fringe, a positioning orifice, a threaded section, and a connection groove. The movable sleeve moves on the body. The handle includes a hollowly circular fitting portion. The switcher includes a coupling portion, a connection flange, a defining hole, and a fitting hole. The drive rod includes a shank, a positioning fringe, and a fixing portion. The transmission shaft includes a threaded orifice, a connecting portion, and a shoulder. The cap is hollow. The locking element includes a threaded extension, a driving portion, and a threaded aperture. The screw nut includes a screwing section and a receiving orifice.
    Type: Application
    Filed: October 1, 2023
    Publication date: April 3, 2025
    Inventor: Wei-Chih Chen
  • Publication number: 20250111123
    Abstract: A method for checking standard cell spacing in a design includes providing a first standard cell. A cell environment of the first standard cell is determined and a first feasible distance between a first boundary of the standard cell and a boundary of a first adjacent cell based on the cell environment is determined. A second feasible distance between a second boundary of the standard cell and a boundary of a second adjacent cell based on the cell environment is determined. A feasible spacing between the first standard cell and a second standard cell is provided, and the feasible spacing is evaluated based on the first feasible distance, the second feasible distance and a cell pitch of the first standard cell. An integrated circuit is fabricated that includes the first standard cell in response on the evaluating.
    Type: Application
    Filed: September 28, 2023
    Publication date: April 3, 2025
    Inventors: Hung-Chih Ou, Yu-Sheng Lu, Wen-Hao Chen
  • Publication number: 20250112548
    Abstract: A power converter and a power conversion method are provided and capable of bus capacitor voltage balance based on inherent inductor components of the power converter. Compared with the conventional approach that adds a balance circuit, the power converter and the power conversion method can reduce a size of overall circuit and improve a power density. In addition, two relays of the power converter are configured to switch switching states such that two inductors store or release energy, thereby transmitting electrical energy between two bus capacitors and two load capacitors. The power converter and the power conversion method are able to realize energy balance and hybrid power supply and satisfy various load requirements.
    Type: Application
    Filed: November 22, 2023
    Publication date: April 3, 2025
    Inventors: Hung-Chieh Lin, Yi-Ping Hsieh, Hsin-Chih Chen, Hung-Yu Huang, Jin-Zhong Huang
  • Publication number: 20250110526
    Abstract: Systems and methods are provided for a clock generator is configured to generate N clock signals evenly spaced by phase. A clock generator includes a poly phase filter configured to utilize a differential clock signal to generate N intermediate signals, the intermediate signals being spaced approximately 360/N degrees apart in phase. A phase error corrector is configured to receive the intermediate signals and to generate N clock output signals, where a phase error is a measure of a difference in phase between consecutive ones of the clock output signals from 360/N degrees, the phase error corrector being configured to reduce phase error among the clock output signals based on a feedback signal. A phase error detection circuit is configured to receive the clock output signals and to generate the feedback signal based on detected phase errors among the clock output signals.
    Type: Application
    Filed: December 13, 2024
    Publication date: April 3, 2025
    Inventor: Wei Chih Chen
  • Publication number: 20250112084
    Abstract: A mechanism for fine adjusting an angle of a semiconductor wafer fixture includes a fixture for a semiconductor wafer, a turntable, a rotating motor and a base. The top surface of the fixture is provided with a positioning portion for accommodating a semiconductor wafer, the turntable is detachably installed under the fixture, the rotating motor connects the bottom of the turntable and is installed on the base. An assembly for fine adjusting an angle of a semiconductor wafer fixture includes the above mechanism and several air bearings installed on the circumferential area of the base to support the turntable so as to fine adjust an angle of the turntable and the fixture.
    Type: Application
    Filed: November 6, 2023
    Publication date: April 3, 2025
    Inventors: Te-Chun CHEN, Ming-Chih CHENG
  • Patent number: 12266148
    Abstract: In various examples, sensor data representative of an image of a field of view of a vehicle sensor may be received and the sensor data may be applied to a machine learning model. The machine learning model may compute a segmentation mask representative of portions of the image corresponding to lane markings of the driving surface of the vehicle. Analysis of the segmentation mask may be performed to determine lane marking types, and lane boundaries may be generated by performing curve fitting on the lane markings corresponding to each of the lane marking types. The data representative of the lane boundaries may then be sent to a component of the vehicle for use in navigating the vehicle through the driving surface.
    Type: Grant
    Filed: May 1, 2023
    Date of Patent: April 1, 2025
    Assignee: NVIDIA Corporation
    Inventors: Yifang Xu, Xin Liu, Chia-Chih Chen, Carolina Parada, Davide Onofrio, Minwoo Park, Mehdi Sajjadi Mohammadabadi, Vijay Chintalapudi, Ozan Tonkal, John Zedlewski, Pekka Janis, Jan Nikolaus Fritsch, Gordon Grigor, Zuoguan Wang, I-Kuei Chen, Miguel Sainz
  • Patent number: 12265119
    Abstract: A socket of a testing tool is configured to provide testing signals. A device-under-test (DUT) board is configured to provide electrical routing. An integrated circuit (IC) die is disposed between the socket and the DUT board. The testing signals are electrically routed to the IC die through the DUT board. The IC die includes a substrate in which plurality of transistors is formed. A first structure contains a plurality of first metallization components. A second structure contains a plurality of second metallization components. The first structure is disposed over a first side of the substrate. The second structure is disposed over a second side of the substrate opposite the first side. A trench extends through the DUT board and extends partially into the IC die from the second side. A signal detection tool is configured to detect electrical or optical signals generated by the IC die.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: April 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chien-Yi Chen, Kao-Chih Liu, Chia Hong Lin, Yu-Ting Lin, Min-Feng Ku
  • Patent number: 12266632
    Abstract: A package structure includes: 1) a circuit substrate; 2) a first semiconductor device disposed on the circuit substrate; 3) a first insulation layer covering a sidewall of the first semiconductor device; 4) a second insulation layer covering the first insulation layer; and 5) a third insulation layer disposed on the circuit substrate and in contact with the second insulation layer.
    Type: Grant
    Filed: January 11, 2022
    Date of Patent: April 1, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chi-Chih Shen, Jen-Chuan Chen, Tommy Pan
  • Patent number: 12265739
    Abstract: The present invention discloses a data access interface unit comprising: a physical storage device controller for receiving a first control signal from a first storage virtualization controller, and accordingly determining the first storage virtualization controller as the primary controller, and generating a first selection signal; a selector for receiving the first selection signal, and accordingly selecting data and signals from the first storage virtualization controller; and a clock generation circuit for providing a dedicated clock signal to the physical storage device, where when the physical storage device controller receives a re-set signal from a second storage virtualization controller, the physical storage device controller determines the second storage virtualization controller as the new primary controller, and accordingly generates a second selection signal so as to control the selector to select data and signals from the second storage virtualization controller.
    Type: Grant
    Filed: November 22, 2023
    Date of Patent: April 1, 2025
    Assignee: Infortrend Technology, Inc.
    Inventors: Yen-Chen Wu, Ying-Wen Lin, Chih-Min Hsiao
  • Patent number: 12266528
    Abstract: A method for forming a patterned mask layer is provided. The method includes forming a layer over a substrate. The method includes forming a first strip structure and a second strip structure over the layer. The method includes forming a spacer layer over the first strip structure, the second strip structure, and the layer. The method includes forming a third strip structure and a fourth strip structure between the first strip part and the second strip part. The connecting part is between the third strip structure and the fourth strip structure. The method includes removing the spacer layer. The first strip structure, the second strip structure, the third strip structure, and the fourth strip structure together form a patterned mask layer.
    Type: Grant
    Filed: July 5, 2023
    Date of Patent: April 1, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Chen Chang, Chien-Wen Lai, Chih-Min Hsiao
  • Patent number: D1070064
    Type: Grant
    Filed: January 13, 2022
    Date of Patent: April 8, 2025
    Assignee: Delta Electronics, Inc.
    Inventors: Chih-Hui Wu, Kuan-Chen Liu