Patents by Inventor Chih-An Chen

Chih-An Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250079997
    Abstract: The present invention provides an isolated power supply having a fast output response, comprising an isolated power supply and a control unit. The isolated power supply includes a primary side power-stage unit, a secondary side power-stage unit, and an isolation transformer, and the control unit includes a primary side control unit, a secondary side control unit, and a photo-coupling isolation unit.
    Type: Application
    Filed: March 27, 2024
    Publication date: March 6, 2025
    Inventors: Yuan-Chih LIN, Xiao-Ze LIN, Ching-Jan CHEN
  • Publication number: 20250075539
    Abstract: A method and structure for reinforcing a car tailgate handle is used to strengthen a tailgate handle that is prone to breaking. Through the steps of disassembly, measurement, production of reinforcement parts, assembly of reinforcement parts and original parts, and installation, it is possible to quickly and extensively remedy tailgate handles with mechanical structural defects that have already been sold. This method and structure offer advantages such as simplified design, reduced material usage, environmental friendliness, ease of production, and rapid mass production.
    Type: Application
    Filed: October 17, 2023
    Publication date: March 6, 2025
    Applicant: HUSHAN AUTOPARTS INC.
    Inventors: Ying-Chih Chen, Ching-Chiang Tsai, Chang-Sheng Su
  • Publication number: 20250073850
    Abstract: A chemical mechanical polishing chamber may include a platen disposed within the chemical mechanical polishing chamber, the platen configured to support a polishing pad. The chamber may also include a slurry delivery arm configured to deliver a slurry to the polishing pad during a chemical mechanical polishing process. The chamber may include an arm may include one or more brackets, mechanically attached to an internal side of the chemical mechanical polishing chamber and positioned over the platen. The chamber may include a plurality of nozzles configured to deliver a gas to the polishing pad, the plurality of nozzles mechanically attached to the one or more brackets of the arm, each of the plurality of nozzles oriented such that an air gap is disposed between adjacent nozzles of the plurality of nozzles such that air may be pulled from the air gap and propelled with the gas towards the polishing pad.
    Type: Application
    Filed: August 21, 2024
    Publication date: March 6, 2025
    Applicant: Applied Materials, Inc.
    Inventors: Haosheng WU, Shou-Sung CHANG, Priscilla DIEP, Hui CHEN, Chih Chung CHOU, Jeonghoon OH, Jianshe TANG, Brian J. BROWN
  • Publication number: 20250081047
    Abstract: A radio access network (RAN); a core network (CN) or operations, administration, and management (OAM) node; and a user equipment (UE) can implement a method for managing Quality of Experience (QoE) reporting from the UE. The method includes: facilitating QoE reporting to a QE node for the UE; determining to perform a handover for the UE from a source node of the RAN to a target node of the RAN; and pausing the QoE reporting. The method may further providing information to identify a QoE configuration of multiple configurations. The information may include QoE configurations, reference identifiers, QoE configuration identifiers, and information about associations between the reference identifiers and the QoE configuration identifiers.
    Type: Application
    Filed: August 5, 2022
    Publication date: March 6, 2025
    Inventors: Chih-Hsiang Wu, Teming Chen
  • Publication number: 20250080129
    Abstract: According to an aspect of the disclosure, the disclosure provides an ADC which includes not limited to: a DAC configured to generate a positive input delta voltage and a negative input delta voltage, a comparator electrically connected to the DAC and configured to receive the positive input delta voltage to generate a first digital output value and to receive the negative input delta voltage to generate a second digital output value, a logic circuit configured to receive, from the comparator, the first digital output value and the second digital output value to generate a digital quantization code according to half of a sum of the first digital output value and the second digital output value, and a calibration circuit configured to receive the digital quantization code from the logic circuit and calibrate an output of the ADC according to the digital quantization code to eliminate an offset error value.
    Type: Application
    Filed: September 11, 2023
    Publication date: March 6, 2025
    Applicant: United Microelectronics Corp.
    Inventors: Hsuan Chih Yeh, Yu-Yee Liow, Wen-Hong Hsu, Po-Hua Chen, Chihwei Wu, Pei Wen Sun
  • Publication number: 20250079237
    Abstract: A metal interconnect structure includes a first metal interconnection in an inter-metal dielectric (IMD) layer on a substrate, a second metal interconnection on the first metal interconnection, and a cap layer between the first metal interconnection and the second metal interconnection. Preferably, a top surface of the first metal interconnection is even with a top surface of the IMD layer and the cap layer is made of conductive material.
    Type: Application
    Filed: November 18, 2024
    Publication date: March 6, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Yi-How Chou, Tzu-Hao Fu, Tsung-Yin Hsieh, Chih-Sheng Chang, Shih-Chun Tsai, Kun-Chen Ho, Yang-Chou Lin
  • Patent number: 12242258
    Abstract: A system for controlling the non-product wafer includes the following: a monitoring module, configured to monitor the state of the non-product wafer; a statistics module, configured to obtain usage information of the non-product wafer; and a control module, configured to receive a production instruction and control the non-product wafer according to the state and the usage information of the non-product wafer. The disclosure implements the purpose of automatic control and management of the non-product wafer.
    Type: Grant
    Filed: March 17, 2022
    Date of Patent: March 4, 2025
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Wei Jiang, Ju-Chieh Chung, Chien-Chih Chen, Delong Huang
  • Patent number: 12243901
    Abstract: A circuit, including: a photodetector including a first readout terminal and a second readout terminal different than the first readout terminal; a first readout circuit coupled with the first readout terminal and configured to output a first readout voltage; a second readout circuit coupled with the second readout terminal and configured to output a second readout voltage; and a common-mode analog-to-digital converter (ADC) including: a first input terminal coupled with a first voltage source; a second input terminal coupled with a common-mode generator, the common-mode generator configured to receive the first readout voltage and the second readout voltage, and to generate a common-mode voltage between the first and second readout voltages; and a first output terminal configured to output a first output signal corresponding to a magnitude of a current generated by the photodetector.
    Type: Grant
    Filed: March 15, 2023
    Date of Patent: March 4, 2025
    Assignee: Artilux, Inc.
    Inventors: Yun-Chung Na, Che-Fu Liang, Shu-Lu Chen, Szu-Lin Cheng, Han-Din Liu, Chien-Lung Chen, Yuan-Fu Lyu, Chieh-Ting Lin, Bo-Jiun Chen, Hui-Wen Chen, Shu-Wei Chu, Chung-Chih Lin, Kuan-Chen Chu
  • Patent number: 12243744
    Abstract: A method for forming a semiconductor structure includes forming first mandrels over a target layer. The method for forming a semiconductor structure also includes forming a first opening to cut off one of the first mandrels. The method for forming a semiconductor structure also includes forming a spacer layer over the first mandrels. The method for forming a semiconductor structure also includes forming second mandrels over the spacer layer and between the first mandrels. The method for forming a semiconductor structure also includes forming a second opening to cut off one of the second mandrels. The method for forming a semiconductor structure also includes etching the spacer layer. The method for forming a semiconductor structure also includes etching the target layer.
    Type: Grant
    Filed: June 12, 2023
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yu-Chen Chang, Chien-Wen Lai, Chih-Min Hsiao
  • Patent number: 12242150
    Abstract: An electronic device includes: a first substrate; a second substrate opposite to the first substrate; a black matrix layer disposed between the first and second substrates and including a first pixel region and a first shielding region arranged along a first direction, wherein the first pixel region includes first and sub-pixel openings arranged along a second direction different from the first direction; a scan line disposed between the first and second substrates and extending along the second direction, wherein the first shielding region overlaps the scan line; and first and second pixel color resists respectively disposed corresponding to the first and second sub-pixel openings, wherein in a cross-sectional view, a recess is formed between the first pixel color resist and the second pixel color resist, the recess is disposed in the first pixel region, and the recess comprises a curved side wall.
    Type: Grant
    Filed: April 12, 2023
    Date of Patent: March 4, 2025
    Assignee: INNOLUX CORPORATION
    Inventors: Wei-Chih Chen, Chih-Ming Liang
  • Publication number: 20250072008
    Abstract: Provided is a semiconductor device including: a substrate, a plurality of isolation structures, a plurality of channel layers, and a gate structure. The substrate includes a plurality of fins thereon. The plurality of isolation structures are respectively disposed between the plurality of fins. A top surface of the plurality of isolation structures is higher than a top surface of the plurality of fins to form a plurality of openings. The plurality of channel layers are respectively disposed in the plurality of openings. Each channel layer is in contact with a corresponding fin and extends to cover a lower sidewall of a corresponding isolation structure, thereby forming a U-shaped structure. The gate structure is filled in the plurality of openings and extends to cover the top surface of the plurality of isolation structures.
    Type: Application
    Filed: November 7, 2024
    Publication date: February 27, 2025
    Applicant: Winbond Electronics Corp.
    Inventors: Chi-Ching Liu, Chih-Chao Huang, Ming-Che Lin, Frederick Chen, Han-Huei Hsu
  • Publication number: 20250071843
    Abstract: A Bluetooth connection system is provided. The Bluetooth connection system includes a control host and a Bluetooth audio device. The control host includes a transmission unit. The Bluetooth audio device wirelessly communicates with the transmission unit, wherein the control host receives an instruction, then turns on the transmission unit and executes a search task to find the Bluetooth audio device around the control host. When the Bluetooth audio device does not return a confirmation Bluetooth connection signal to the control host, the control host sends a wake-up signal to the Bluetooth audio device to start a re-pairing procedure.
    Type: Application
    Filed: July 2, 2024
    Publication date: February 27, 2025
    Applicant: BENQ CORPORATION
    Inventors: Chih-Hung LIN, Chen-Chen TSAI
  • Publication number: 20250066100
    Abstract: Equipment adapted for a waste volume expansion stabilization process has an autoclave and a waste carrying container. The waste carrying container is configured for carrying a pile of waste, is positioned in the autoclave, and has a chamber and a steam conducting unit installed in the chamber and having multiple steam tubes. Each steam tube connects with the autoclave via a first opening thereof and connects with the chamber via a second opening thereof. High pressure steam flows into the steam tubes from the first openings and flows into the chamber to be mixed with the pile of the waste via the second opening. Surface contact areas between the steam and the pile of waste is increased. The performance of the waste volume expansion stabilization process is improved and processing time for the waste volume expansion stabilization process can be reduced.
    Type: Application
    Filed: August 25, 2023
    Publication date: February 27, 2025
    Inventors: Kenneth Fang, Wei-Chih Chen
  • Publication number: 20250071983
    Abstract: A method for fabricating a semiconductor device includes the steps of first providing a substrate having a transistor region and an one time programmable (OTP) capacitor region, forming a first fin-shaped structure on the transistor region and a second fin-shaped structure on the OTP capacitor region, and then performing an oxidation process to form a gate oxide layer on the first fin-shaped structure and the second fin-shaped structure. Preferably, the first fin-shaped structure and the second fin-shaped structure have different shapes under a cross-section perspective.
    Type: Application
    Filed: September 24, 2023
    Publication date: February 27, 2025
    Applicant: UNITED MICROELECTRONICS CORP.
    Inventors: Kuo-Hsing Lee, Sheng-Yuan Hsueh, Yung-Chen Chiu, Chih-Kai Kang, Wen-Kai Lin
  • Publication number: 20250068811
    Abstract: An integrated circuit design implementation system includes a synthesis tool configured to: receive a behavioral description of each of a plurality of first components; generate first netlists based on the behavioral descriptions of the first components; receive connection information of a plurality of second components, wherein the connection information comprises physical arrangement and connectivity among the first components and the second components; generate a plurality of third components, wherein each of the third components operatively corresponds to an interface between a pair of one of the first components and one of the second components; and transform the first netlists to a second netlist based on first vertices, second vertices, third vertices, and edges. The first vertices correspond to the first components, respectively, the second vertices correspond to the second components, respectively, and the third vertices correspond to the third components, respectively.
    Type: Application
    Filed: August 23, 2023
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Ching-Fang Chen, Ang-Chih Hsieh, Wei-Heng Lo, Heng-Yi Lin, Chih-Wei Chang
  • Publication number: 20250072082
    Abstract: A semiconductor device includes: first and second fin structures, disposed on a substrate, that respectively extend in parallel to an axis; a first gate feature that traverses the first fin structure to overlay a central portion of the first fin structure; a second gate feature that traverses the second fin structure to overlay a central portion of the second fin structure; a first spacer comprising: a first portion comprising two layers that respectively extend from sidewalls of the first gate feature toward opposite directions of the axis; and a second portion comprising two layers that respectively extend from sidewalls of the first portion of the first spacer toward the opposite directions of the axis; and a second spacer comprising two layers that respectively extend from sidewalls of the second gate feature toward the opposite directions of the axis.
    Type: Application
    Filed: November 5, 2024
    Publication date: February 27, 2025
    Inventors: I-Chih CHEN, Ru-Shang HSIAO, Ching-Pin LIN, Chih-Mu HUANG, Fu-Tsun TSAI
  • Publication number: 20250068048
    Abstract: A projection device and an auto-focus method of the projection device are provided. A projection distance between a projection lens of the projection device and a projection surface is detected to generate a distance detection signal. A control unit updates an expanded look-up table based on the original look-up table, the distance detection signal, an optimal motor step, and an adjustment completion time, where the optimal motor step and the adjustment completion time are obtained through a manual focus operation. An auto-focus operation is performed based on the distance detection signal and the updated expanded look-up table.
    Type: Application
    Filed: August 5, 2024
    Publication date: February 27, 2025
    Applicant: Coretronic Corporation
    Inventor: Chih-Chen Chen
  • Publication number: 20250069989
    Abstract: A semiconductor device includes a FEOL structure and a BEOL structure. The BEOL structure is formed over the FEOL structure and includes a conductive layer, an etching stop layer (ESL) structure, a through via and a barrier layer. The ESL structure is formed over the conductive layer and has a first recess and a lateral surface. The through via passes through the ESL structure to form the first recess and the lateral surface. The barrier layer covers the lateral surface and the first recess. The first recess is recessed with respect to the lateral surface, and the first recess has a first depth ranging between 1 nm and 7 nm.
    Type: Application
    Filed: August 25, 2023
    Publication date: February 27, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yen-Chih HUANG, Li-An SUN, Chih-Hao CHEN, Chung-Chuan HUANG
  • Publication number: 20250071912
    Abstract: A method of manufacturing an electronic device is provided. The method includes providing a substrate, disposing a composite conductive layer on the substrate, and patterning the composite conductive layer into a composite conductive pattern in two wet etching steps. Moreover, the two wet etching steps use different etching solutions.
    Type: Application
    Filed: July 24, 2024
    Publication date: February 27, 2025
    Inventors: Ming-Chih TSAI, Yu-Heng CHEN
  • Patent number: 12237218
    Abstract: A method of fabricating a contact structure includes the following steps. An opening is formed in a dielectric layer. A conductive material layer is formed within the opening and on the dielectric layer, wherein the conductive material layer includes a bottom section having a first thickness and a top section having a second thickness, the second thickness is greater than the first thickness. A first treatment is performed on the conductive material layer to form a first oxide layer on the bottom section and on the top section of the conductive material layer. A second treatment is performed to remove at least portions of the first oxide layer and at least portions of the conductive material layer, wherein after performing the second treatment, the bottom section and the top section of the conductive material layer have substantially equal thickness.
    Type: Grant
    Filed: May 6, 2022
    Date of Patent: February 25, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chang-Ting Chung, Shih-Wei Yeh, Kai-Chieh Yang, Yu-Ting Wen, Yu-Chen Ko, Ya-Yi Cheng, Min-Hsiu Hung, Chun-Hsien Huang, Wei-Jung Lin, Chih-Wei Chang, Ming-Hsing Tsai