Patents by Inventor Chih-An Chen

Chih-An Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12099301
    Abstract: A method of manufacturing a semiconductor device includes forming a photoresist underlayer over a semiconductor substrate. The photoresist underlayer includes a polymer, including a main polymer chain having pendant target groups, and pendant organic groups or photoacid generator groups. The main polymer chain is a polystyrene, a polyhydroxystyrene, a polyacrylate, a polymethylacrylate, a polymethylmethacrylate, a polyacrylic acid, a polyvinyl ester, a polymaleic ester, a poly(methacrylonitrile), or a poly(methacrylamide). Pendant target groups are selected from the group consisting of a substituted or unsubstituted: C2-C30 diol group, C1-C30 aldehyde group, and C3-C30 ketone group. Pendant organic groups are C3-C30 aliphatic or aromatic groups having at least one photosensitive functional group, and pendant photoacid generator groups are C3-C50 substituted aliphatic or aromatic groups. A photoresist layer is formed over the photoresist underlayer.
    Type: Grant
    Filed: April 15, 2021
    Date of Patent: September 24, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Chien-Chih Chen
  • Patent number: 12100991
    Abstract: A dual-input power switching system includes a first DC power source, a second DC power source, a DC conversion circuit, and a boost-up circuit. The first DC power source provides a first DC voltage, and the second DC power source provides a second DC voltage. The DC conversion circuit receives the first DC voltage or the second DC voltage being an input voltage, and converts the input voltage to supply power to a load. The boost-up circuit provides a hold-up voltage to boost up the input voltage when the first DC power source stops supplying power to lead to power drop of the input voltage, such that the input voltage reaches to a specific voltage that is greater than the second DC voltage and afterward naturally decreases to be less than or equal to the second DC voltage.
    Type: Grant
    Filed: August 11, 2022
    Date of Patent: September 24, 2024
    Assignee: DELTA ELECTRONICS, INC.
    Inventors: Yuan-Fang Lee, Chang-Chih Chen, Chih-Chiang Chan
  • Publication number: 20240310926
    Abstract: A composite function keyboard circuit includes a first matrix circuit, a first bias resistor group, a second matrix circuit, a second bias resistor group and a controller. Each switch unit in the first matrix circuit is an ink-type force sensing switch. A resistance of the ink-type force sensing switch is variable according to a pressing mode of a keypress action. An electrical connection path is formed between the ink-type force sensing switch and the corresponding bias resistor of the second bias resistor group. When the ink-type force sensing switch is electrically conducted, a divided sensing voltage is generated by the electrical connection path, and the controller generates a corresponding key control instruction according to a level of the divided sensing voltage. Furthermore, the cooperation of the first matrix circuit and the first bias resistor group can achieve a ghost key preventing function.
    Type: Application
    Filed: May 4, 2023
    Publication date: September 19, 2024
    Inventors: Yi-Liang Chen, Chih-Chen Chang, Chien-Ming Li
  • Publication number: 20240313047
    Abstract: A semiconductor device structure includes first nanostructures and second nanostructures formed over a substrate. The structure also includes gate structures that are wrapped around the first nanostructures and the second nanostructures and that extend along a first direction. The structure also includes a dielectric structure formed between two of the gate structures and parallel to the gate structures. A first sidewall of the first nanostructures is shifted from a first sidewall of the second nanostructures in a second direction, the second direction is different from the first direction.
    Type: Application
    Filed: March 14, 2023
    Publication date: September 19, 2024
    Inventors: Hong-Chih CHEN, Chun-Yi CHANG, Fu-Hsiang SU, Shih-Hsun CHANG
  • Publication number: 20240312874
    Abstract: A semiconductor structure includes a substrate, a through via penetrating the substrate, a trench capacitor, a first redistribution layer (RDL), a second RDL, and a contact feature. The trench capacitor extends from a back surface toward a front surface of the substrate, wherein the trench capacitor is separated from an active area at the front surface of the substrate. The first RDL is disposed over the front surface and electrically connecting to the through via, wherein the active area is disposed between the trench capacitor and the first RDL. The second RDL is disposed over the back surface and electrically connecting to the through via and the trench capacitor. The contact feature is disposed over the first RDL and electrically connecting to the trench capacitor through the first RDL, the through via and the second RDL. A method of manufacturing the semiconductor structure is also provided.
    Type: Application
    Filed: June 25, 2023
    Publication date: September 19, 2024
    Inventors: TZU-WEI CHIU, CHUN-WEI CHANG, WEI-CHIH CHEN, CHE-YEN HUANG
  • Publication number: 20240312891
    Abstract: A semiconductor structure includes a plurality of dies over a redistribution layer (RDL). A first die comprises: a first substrate; a first (RDL), disposed over a front surface of the first substrate; and a first back-side through via (BSTV), extending from a back surface of the first substrate toward the front surface of the first substrate. A second die, adjacent to the first die and separated from the first die by a molding material, comprises: a second substrate; a second RDL, disposed over a front surface of the second substrate; and a second BSTV, extending from a back surface of the second substrate toward the front surface of the second substrate. The RDL continuously covers the back surfaces of the first and second substrates, and electrically connects the first RDL to the second RDL via the first and second BSTVs. A method of manufacturing the semiconductor structure is also provided.
    Type: Application
    Filed: September 13, 2023
    Publication date: September 19, 2024
    Inventors: TZU-WEI CHIU, CHUN-WEI CHANG, WEI-CHIH CHEN, CHE-YEN HUANG
  • Patent number: 12095364
    Abstract: A down-converted voltage regulator is provided. The first energy storage element provides a pre-charged voltage between a connection terminal and a ground terminal during the first phase. The second energy storage element has a first terminal, and it has a second terminal coupled to the output terminal of the voltage regulator. The third energy storage element is coupled between the output terminal of the voltage regulator and the ground terminal. During the first phase, the first terminal of the second energy storage element is coupled to the first energy storage element through the connection terminal to receive the pre-charged voltage. During the second phase, the first energy storage element is coupled between the input terminal and the output terminal of the voltage regulator to be pre-charged to store the pre-charged voltage, and the first terminal of the second energy storage element is coupled to the ground terminal.
    Type: Grant
    Filed: December 9, 2022
    Date of Patent: September 17, 2024
    Assignee: MEDIATEK INC.
    Inventors: Chih-Chen Li, Jin-Yan Syu
  • Patent number: 12094838
    Abstract: In some embodiments, the present disclosure relates to a semiconductor structure. The semiconductor structure includes a stacked semiconductor substrate having a semiconductor material disposed over a base semiconductor substrate. The base semiconductor substrate has a first coefficient of thermal expansion and the semiconductor material has a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion. The stacked semiconductor substrate includes one or more sidewalls defining a crack stop ring trench that continuously extends in a closed path between a central region of the stacked semiconductor substrate and a peripheral region of the stacked semiconductor substrate surrounding the central region. The peripheral region of the stacked semiconductor substrate includes a plurality of cracks and the central region is substantially devoid of cracks.
    Type: Grant
    Filed: July 20, 2023
    Date of Patent: September 17, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jiun-Yu Chen, Chun-Lin Tsai, Yun-Hsiang Wang, Chia-Hsun Wu, Jiun-Lei Yu, Po-Chih Chen
  • Publication number: 20240303882
    Abstract: Embodiments described herein provide a feedback based instructional image editing framework that employs a diffusion process to follow user instruction for image editing. A diffusion model is fine-tuned using a reward model, which may be trained via human annotation. The training of the reward model may be done by having the image editing model output a number of images, which a human annotator ranks based on their alignment with the original image and a given instruction.
    Type: Application
    Filed: July 12, 2023
    Publication date: September 12, 2024
    Inventors: Shu Zhang, Xinyi Yang, Yihao Feng, Ran Xu, Ning Yu, Chia-Chih Chen
  • Publication number: 20240304511
    Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes a semiconductor die and a redistribution structure disposed on the semiconductor die. The redistribution structure includes an alignment auxiliary layer, a plurality of dielectric layers and a plurality of conductive patterns. The alignment auxiliary layer has a light transmittance for a light with a wavelength range of about 350-550 nm lower than that of one of the plurality of dielectric layers.
    Type: Application
    Filed: March 10, 2023
    Publication date: September 12, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Yu-Hsiang Hu, Hung-Jui Kuo, Po-Han Wang, Hung-Chun Cho
  • Publication number: 20240297217
    Abstract: A method for forming a semiconductor structure is provided. The method includes forming an active region including a lower fin element and first semiconductor layers and second semiconductor layers alternately stacked over the lower fin element, forming a fin spacer layer along a sidewall of the active region, forming a dielectric wall over the fin spacer layer, forming a dummy gate structure over the active region, the fin spacer layer and the dielectric wall, and etching the active region, the fin spacer layer, and the first dielectric wall to form a first recess. The method also includes laterally recessing, from the first recess, the first semiconductor layers of the active region and the fin spacer layer to form a notch, forming an inner spacer layer in the notch, and forming a source/drain feature on the lower fin element of the active region.
    Type: Application
    Filed: March 3, 2023
    Publication date: September 5, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hong-Chih CHEN, Chun-Sheng LIANG, Jhon-Jhy LIAW, Fu-Hsiang SU
  • Publication number: 20240295823
    Abstract: A method for manufacturing an electronic device is provided. In the method for manufacturing an electronic device, a substrate is provided, a device layer is disposed on the substrate, and a photoresist layer is disposed on the device layer. Next, a photo mask is disposed on the photoresist layer, and a light source is used to firstly illuminate the photo mask to form a first exposure region. After that, a relative movement is made between the substrate and the photo mask, and the light source is used to secondly illuminate the photo mask to form a second exposure region, wherein the first exposure region partially overlaps the second exposure region. Afterwards, a pattern is developed on the substrate, the device layer is etched using a patterned photoresist layer as an etching mask, and then the patterned photoresist layer is removed.
    Type: Application
    Filed: May 13, 2024
    Publication date: September 5, 2024
    Applicant: Innolux Corporation
    Inventors: Chun-Yuan Chuang, Ming-Chih Chen, Jean Huang, Wei-Jen Wang, Tao-Lung Cheng
  • Publication number: 20240296296
    Abstract: Embodiments of the present disclosure relate to a method, system, and computer program product for translation of rich text. In some embodiments, a method is disclosed. According to the method, one or more candidate formats are determined for source rich text. A target format for the source rich text is selected from the one or more candidate formats based on one or more corresponding images obtained from rendering the source rich text in the one or more candidate formats. Based on the target format, a translation editing environment is provided for editing a translation of the source rich text. In other embodiments, a system and a computer program product are disclosed.
    Type: Application
    Filed: March 2, 2023
    Publication date: September 5, 2024
    Inventors: Jin Shi, CHIH-YUAN LIN, Shu-Chih Chen, PEI-YI LIN, Chao Yuan Huang
  • Publication number: 20240293536
    Abstract: The present invention relates to a porcine bivalent subunit vaccine composition in a single dose. The porcine bivalent subunit vaccine composition includes porcine bivalent antigen, CpG adjuvant and a dual phase adjuvant. The porcine bivalent antigen consists of a classical swine fever virus (CSFV)-E2 recombinant protein and a porcine circovirus type 2 (PCV2)-ORF2 recombinant protein, both of which are produced by a mammalian cell expression system. The porcine bivalent subunit vaccine composition in a single dose can confer effectively immune protection against CSFV and PCV2 via a single vaccination without boost vaccination.
    Type: Application
    Filed: December 22, 2023
    Publication date: September 5, 2024
    Applicant: National Pingtung University Of Science And Technology
    Inventors: Hso-Chi Chaung, Wen-Bin Chung, Yen-Li Huang, Chi-Chih Chen, Yu-Chieh Chen
  • Publication number: 20240290588
    Abstract: An ion collector includes a plurality of segments and a plurality of integrators. The plurality of segments are physically separated from one another and spaced around a substrate support. Each of the segments includes a conductive element that is designed to conduct a current based on ions received from a plasma. Each of the plurality of integrators is coupled to a corresponding conductive element. Each of the plurality of integrators is designed to determine an ion distribution for a corresponding conductive element based, at least in part, on the current conducted at the corresponding conductive element. An example benefit of this embodiment includes the ability to determine how uniform the ion distribution is across a wafer being processed by the plasma.
    Type: Application
    Filed: May 3, 2024
    Publication date: August 29, 2024
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Otto CHEN, Chi-Ying WU, Chia-Chih CHEN
  • Publication number: 20240280886
    Abstract: A lens module includes a lens assembly, an actuator, an encoder, and a controller. The actuator is connected to the lens assembly. The encoder is connected to the actuator and linked with the actuator. The encoder includes a first portion and a second portion. The first portion includes multiple areas, and each of the areas includes at least one conductor. The second portion includes multiple conductive contacts. When the actuator drives the encoder to move, the second portion moves relative to the first portion, and the encoder outputs a voltage signal according to whether the conductive contacts are in contact with the at least one conductor in the areas. The controller is electrically connected to the encoder and the actuator. The controller determines a state of the encoder according to the voltage signal. A projection device and a method for adjusting the lens module are also disclosed.
    Type: Application
    Filed: February 19, 2024
    Publication date: August 22, 2024
    Applicant: Coretronic Corporation
    Inventors: Chia-Ching Liao, Hui-Ju Lin, Chih-Chen Chen, Tung-Yi Ko
  • Publication number: 20240281612
    Abstract: A method, computer system, and a computer program product for task assistance is provided. The present invention may include acquiring a request expression input by a user. The present invention may include identifying a request intent associated with a task based on the request expression. The present invention may include determining a response script corresponding to the request intent. The present invention may include executing the response script to complete the task and presenting the process of running the task in a user-interface (UI).
    Type: Application
    Filed: February 21, 2023
    Publication date: August 22, 2024
    Inventors: Jin Shi, CHIH-YUAN LIN, Shu-Chih Chen, Chao Yuan Huang, PEI-YI LIN
  • Patent number: 12068331
    Abstract: An electronic device having a peripheral area and a non-peripheral area adjacent to the peripheral area is provided. The electronic device includes a flexible substrate, a first conductive layer disposed on the flexible substrate and disposed in the peripheral area and the non-peripheral area, an organic layer disposed in the non-peripheral area and on the first conductive layer, a second conductive layer disposed on the first conductive layer, and an organic structure disposed between the first conductive layer and the second conductive layer in the peripheral area. The organic layer and the organic structure are the same material layer.
    Type: Grant
    Filed: April 21, 2023
    Date of Patent: August 20, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Ti-Chung Chang, Chih-Chieh Wang, Chien-Chih Chen
  • Publication number: 20240274560
    Abstract: An integrated circuit structure is provided. The integrated circuit structure includes a die that contains a substrate, an interconnection structure, active connectors and dummy connectors. The interconnection structure is disposed over the substrate. The active connectors and the dummy connectors are disposed over the interconnection structure. The active connectors are electrically connected to the interconnection structure, and the dummy connectors are electrically insulated from the interconnection structure.
    Type: Application
    Filed: April 22, 2024
    Publication date: August 15, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Chao Mao, Chin-Chuan Chang, Szu-Wei Lu, Kun-Tong Tsai, Hung-Chih Chen
  • Patent number: 12061560
    Abstract: A method of a pointing device which is used to be coupled to a host system through a universal serial bus (USB) communication interface includes: providing a USB driver device to communicate with the host system via the USB communication interface; monitoring a specific voltage change or a specific data transmission state of the USB communication interface to generate a monitoring result; and correcting a USB state of the USB driver device when the monitoring result indicates that a undefined or abnormal behavior of the host system occurs.
    Type: Grant
    Filed: June 21, 2023
    Date of Patent: August 13, 2024
    Assignee: PixArt Imaging Inc.
    Inventors: Ching-Chih Chen, Jr-Yi Li