Patents by Inventor Chi HAO

Chi HAO has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240153823
    Abstract: A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.
    Type: Application
    Filed: January 18, 2024
    Publication date: May 9, 2024
    Inventors: Pei Ying Lai, Chia-Wei Hsu, Cheng-Hao Hou, Xiong-Fei Yu, Chi On Chui
  • Publication number: 20240148280
    Abstract: An implantable micro-biosensor a substrate, a first electrode, a second electrode, a third electrode, and a chemical reagent layer. The first electrode is disposed on the substrate and used as a counter electrode. The second electrode is disposed on the substrate and spaced apart from the first electrode. The third electrode is disposed on the substrate and used as a working electrode. The chemical reagent layer at least covers a sensing section of the third electrode so as to permit the third electrode to selectively cooperate with the first electrode or the first and second electrodes to measure a physiological signal in response to the physiological parameter of the analyte.
    Type: Application
    Filed: January 16, 2024
    Publication date: May 9, 2024
    Inventors: Chun-Mu Huang, Chieh-Hsing Chen, Heng-Chia Chang, Chi-Hao Chen, Chien-Chung Chen
  • Publication number: 20240150590
    Abstract: A coated substrate for an electronic device can include a substrate, a basecoat layer on the substrate, and an anti-fingerprint topcoat layer on the basecoat layer. The substrate can include a metal or metal alloy. The basecoat layer can include pigment particles and a first one-part thermally cured polymeric resin. The anti-fingerprint topcoat layer can include a second one-part thermally cured polymeric resin and an anti-fingerprint material. The anti-fingerprint material can include a fluoropolymer, a silane, or a combination thereof. The basecoat layer can be cured before applying the anti-fingerprint topcoat layer on the basecoat layer.
    Type: Application
    Filed: March 18, 2021
    Publication date: May 9, 2024
    Inventors: Kuan-Ting WU, Yong-Jun LI, Chi Hao CHANG, Xiao-Jun ZHU
  • Publication number: 20240153821
    Abstract: Provided are a package structure having stacked semiconductor dies with wavy sidewalls and a method of forming the same. The package structure includes: a first die and a second die bonded together; a first encapsulant laterally encapsulating the first die; and a second encapsulant laterally encapsulating the second die, wherein a second interface of the second die in contact with the second encapsulant is a wavy interface in a cross-sectional plane.
    Type: Application
    Filed: February 23, 2023
    Publication date: May 9, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chen-Shien CHEN, Chi-Yen Lin, Hsu-Hsien Chen, Ting Hao Kuo, Chang-Ching Lin
  • Patent number: 11978714
    Abstract: A method includes bonding a first device die and a second device die to an interconnect die. The interconnect die includes a first portion over and bonded to the first device die, and a second portion over and bonded to the second device die. The interconnect die electrically connects the first device die to the second device die. The method further includes encapsulating the interconnect die in an encapsulating material, and forming a plurality of redistribution lines over the interconnect die.
    Type: Grant
    Filed: December 19, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Kuo-Chiang Ting, Chi-Hsi Wu, Shang-Yun Hou, Tu-Hao Yu, Chia-Hao Hsu, Ting-Yu Yeh
  • Patent number: 11974842
    Abstract: An implantable micro-biosensor a substrate, a first electrode, a second electrode, a third electrode, and a chemical reagent layer. The first electrode is disposed on the substrate and used as a counter electrode. The second electrode is disposed on the substrate and spaced apart from the first electrode. The third electrode is disposed on the substrate and used as a working electrode. The chemical reagent layer at least covers a sensing section of the third electrode so as to permit the third electrode to selectively cooperate with the first electrode or the first and second electrodes to measure a physiological signal in response to the physiological parameter of the analyte.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: May 7, 2024
    Assignee: Bionime Corporation
    Inventors: Chun-Mu Huang, Chieh-Hsing Chen, Heng-Chia Chang, Chi-Hao Chen, Chien-Chung Chen
  • Patent number: 11978782
    Abstract: The present disclosure relates to a hybrid integrated circuit. In one implementation, an integrated circuit may have a first region with a first gate structure having a ferroelectric gate dielectric, at least one source associated with the first gate of the first region, and at least one drain associated with the first gate structure of the first region. Moreover, the integrated circuit may have a second region with a second gate structure having a high-? gate dielectric, at least one source associated with the second gate structure of the second region, and at least one drain associated with the second gate structure of the second region. The integrated circuit may further have at least one trench isolation between the first region and the second region.
    Type: Grant
    Filed: June 9, 2022
    Date of Patent: May 7, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chi-Yi Chuang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang
  • Publication number: 20240143166
    Abstract: The present disclosure is directed to positioning animated images within a dynamic keyboard interface. In particular, the methods and systems of the present disclosure can: receive, from a user device on which an application is executed, data indicating a context of: the application, and/or a dynamic keyboard interface provided in association with the application; identify, based at least in part on the data indicating the context, a plurality of different animated images, including an animated image comprising an advertisement, for presentation by the dynamic keyboard interface; communicate, to the user device, data indicating the plurality of different animated images; receive, from the user device, data indicating a selection of the animated image comprising the advertisement; and determine, based at least in part on the data indicating the selection and the data indicating the context, a position within the dynamic keyboard interface for presenting the animated image comprising the advertisement.
    Type: Application
    Filed: January 11, 2024
    Publication date: May 2, 2024
    Inventors: David McIntosh, Peter Chi Hao Huang, Erick Hachenburg, David Lindsay Bowen, Joseph Lieu, Kira Lee Psomas, Jason R. Krebs, Kumar Garapaty, Samantha Janelle Jiwei Lau
  • Patent number: 11973113
    Abstract: Provided is a semiconductor device including a substrate having a lower portion and an upper portion on the lower portion; an isolation region disposed on the lower portion of the substrate and surrounding the upper portion of the substrate in a closed path; a gate structure disposed on and across the upper portion of the substrate; source and/or drain (S/D) regions disposed in the upper portion of the substrate at opposite sides of the gate structure; and a channel region disposed below the gate structure and abutting between the S/D regions, wherein the channel region and the S/D regions have different conductivity types, and the channel region and the substrate have the same conductivity type.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chung Chen, Chi-Feng Huang, Victor Chiang Liang, Chung-Hao Chu
  • Publication number: 20240130614
    Abstract: An intraocular pressure inspection device includes an intraocular pressure detection unit, a high-precision positioning system and a wide-area positioning system, wherein according to the position of the intraocular pressure detection unit, a set of high-precision coordinates output by the high-precision positioning system and a set of wide-area coordinates output by the wide-area positioning system are integrated in appropriate weights to obtain a set of more precise integrated coordinate. The above-mentioned intraocular pressure inspection device can prevent the intraocular pressure detection unit from failing to operate once it is not in the working area of the high-precision positioning system.
    Type: Application
    Filed: October 13, 2023
    Publication date: April 25, 2024
    Inventors: Shao Hung HUANG, Chao-Ting CHEN, Fong Hao KUO, Yu-Chung TUNG, Chu-Ming CHENG, Chi-Yuan KANG
  • Publication number: 20240136291
    Abstract: Semiconductor devices and methods of forming the same are provided. In some embodiments, a method includes receiving a workpiece having a redistribution layer disposed over and electrically coupled to an interconnect structure. In some embodiments, the method further includes patterning the redistribution layer to form a recess between and separating a first conductive feature and a second conductive feature of the redistribution layer, where corners of the first conductive feature and the second conductive feature are defined adjacent to and on either side of the recess. The method further includes depositing a first dielectric layer over the first conductive feature, the second conductive feature, and within the recess. The method further includes depositing a nitride layer over the first dielectric layer. In some examples, the method further includes removing portions of the nitride layer disposed over the corners of the first conductive feature and the second conductive feature.
    Type: Application
    Filed: January 12, 2023
    Publication date: April 25, 2024
    Inventors: Hsiang-Ku SHEN, Chen-Chiu HUANG, Chia-Nan LIN, Man-Yun WU, Wen-Tzu CHEN, Sean YANG, Dian-Hao CHEN, Chi-Hao CHANG, Ching-Wei LIN, Wen-Ling CHANG
  • Publication number: 20240135976
    Abstract: A memory includes a memory array and a single-ended sense amplifier circuit. The memory array includes wordlines, bitlines, and memory cells. The bitlines include a first bitline, routed on a first metal layer but not a second metal layer, and a second bitline, routed on the first metal layer and the second metal layer. Each of the memory cells is coupled to one of the wordlines. The memory cells include a first group of memory cells, coupled to the first bitline, and a second group of memory cells, coupled to the second bitline, where the first group of memory cells and the second group of memory cells are located at a same column. The single-ended sense amplifier circuit performs a read operation upon a target memory cell through single-ended sensing when a selected wordline is enabled.
    Type: Application
    Filed: September 20, 2023
    Publication date: April 25, 2024
    Applicant: MEDIATEK INC.
    Inventor: Chi-Hao Hong
  • Publication number: 20240136428
    Abstract: Improved inner spacers for semiconductor devices and methods of forming the same are disclosed.
    Type: Application
    Filed: January 2, 2024
    Publication date: April 25, 2024
    Inventors: Wen-Kai Lin, Che-Hao Chang, Chi On Chui, Yung-Cheng Lu
  • Patent number: 11967570
    Abstract: A semiconductor package includes a base comprising a top surface and a bottom surface that is opposite to the top surface; a first semiconductor chip mounted on the top surface of the base in a flip-chip manner; a second semiconductor chip stacked on the first semiconductor chip and electrically coupled to the base by wire bonding; an in-package heat dissipating element comprising a dummy silicon die adhered onto the second semiconductor chip by using a high-thermal conductive die attach film; and a molding compound encapsulating the first semiconductor die, the second semiconductor die, and the in-package heat dissipating element.
    Type: Grant
    Filed: March 4, 2022
    Date of Patent: April 23, 2024
    Assignee: MediaTek Inc.
    Inventors: Chia-Hao Hsu, Tai-Yu Chen, Shiann-Tsong Tsai, Hsing-Chih Liu, Yao-Pang Hsu, Chi-Yuan Chen, Chung-Fa Lee
  • Patent number: 11964201
    Abstract: A modular pneumatic somatosensory device comprises a main body, a plurality of airbags, a plurality of inflating modules and a control module. The airbags are detachably disposed at different positions of the main body, and at least a part of the airbags have different sizes. The inflating modules are detachably disposed on the main body, and each inflating module is correspondingly connected with at least one of the airbags. The control module is detachably disposed on the main body and is electrically connected with the inflating modules. The control module controls the inflating modules to inflate the corresponding airbags according to a control signal.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: April 23, 2024
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Jen-Hui Chuang, June-Hao Hou, Chi-Li Cheng, Han-Ting Lin
  • Publication number: 20240124292
    Abstract: An auxiliary operation device for a droplet dispenser includes a droplet sensor, an imaging device and a processor. The droplet sensor has a detected area located between a droplet dispenser and a target area, wherein the droplet sensor detects a droplet output from the droplet dispenser, and outputs a corresponding droplet detection signal. The imaging device captures an image of the target area. The processor obtains a dripping time point at which the droplet passes through the detected area according to the droplet detection signal, and determines whether the target area is shielded within a first time range according to the image, so as to evaluate whether the droplet has successfully dropped into the target area. The above-mentioned auxiliary operating device of the droplet dispenser can objectively determine whether the droplets successfully drops into the target area, and improve the accuracy of judgment.
    Type: Application
    Filed: October 13, 2023
    Publication date: April 18, 2024
    Inventors: SHAO HUNG HUANG, CHAO-TING CHEN, FONG HAO KUO, CHI-YUAN KANG, Chang Mu WU
  • Patent number: 11961897
    Abstract: A first fin structure is disposed over a substrate. The first fin structure contains a semiconductor material. A gate dielectric layer is disposed over upper and side surfaces of the first fin structure. A gate electrode layer is formed over the gate dielectric layer. A second fin structure is disposed over the substrate. The second fin structure is physically separated from the first fin structure and contains a ferroelectric material. The second fin structure is electrically coupled to the gate electrode layer.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chi-Hsing Hsu, Sai-Hooi Yeong, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao
  • Patent number: 11950902
    Abstract: The present invention provides a micro biosensor for reducing a measurement interference when measuring a target analyte in the biofluid, including: a substrate; a first working electrode configured on the surface, and including a first sensing section; a second working electrode configured on the surface, and including a second sensing section which is configured adjacent to at least one side of the first sensing section; and a chemical reagent covered on at least a portion of the first sensing section for reacting with the target analyte to produce a resultant. When the first working electrode is driven by a first working voltage, the first sensing section measures a physiological signal with respect to the target analyte. When the second working electrode is driven by a second working voltage, the second conductive material can directly consume the interferant so as to continuously reduce the measurement inference of the physiological signal.
    Type: Grant
    Filed: July 31, 2020
    Date of Patent: April 9, 2024
    Assignee: Bionime Corporation
    Inventors: Chun-Mu Huang, Chieh-Hsing Chen, Heng-Chia Chang, Chi-Hao Chen, Pi-Hsuan Chen
  • Publication number: 20240112959
    Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.
    Type: Application
    Filed: December 1, 2023
    Publication date: April 4, 2024
    Inventors: Kuan-Ting PAN, Zhi-Chang LIN, Yi-Ruei JHAN, Chi-Hao WANG, Huan-Chieh SU, Shi Ning JU, Kuo-Cheng CHIANG
  • Publication number: 20240112924
    Abstract: An integrated circuit package including integrated circuit dies with slanted sidewalls and a method of forming are provided. The integrated circuit package may include a first integrated circuit die, a first gap-fill dielectric layer around the first integrated circuit die, a second integrated circuit die underneath the first integrated circuit die, and a second gap-fill dielectric layer around the second integrated circuit die. The first integrated circuit die may include a first substrate, wherein a first angle is between a first sidewall of the first substrate and a bottom surface of the first substrate, and a first interconnect structure on the bottom surface of the first substrate, wherein a second angle is between a first sidewall of the first interconnect structure and the bottom surface of the first substrate. The first angle may be larger than the second angle.
    Type: Application
    Filed: January 5, 2023
    Publication date: April 4, 2024
    Inventors: Hsu-Hsien Chen, Chen-Shien Chen, Ting Hao Kuo, Chi-Yen Lin, Yu-Chih Huang