Abstract: The present invention provides a micro biosensor for reducing a measurement interference when measuring a target analyte in the biofluid, including: a substrate; a first working electrode configured on the surface, and including a first sensing section; a second working electrode configured on the surface, and including a second sensing section which is configured adjacent to at least one side of the first sensing section; and a chemical reagent covered on at least a portion of the first sensing section for reacting with the target analyte to produce a resultant. When the first working electrode is driven by a first working voltage, the first sensing section measures a physiological signal with respect to the target analyte. When the second working electrode is driven by a second working voltage, the second conductive material can directly consume the interferant so as to continuously reduce the measurement inference of the physiological signal.

Abstract: A method of fabricating a device includes forming a dummy gate over a plurality of fins. Thereafter, a first portion of the dummy gate is removed to form a first trench that exposes a first hybrid fin and a first part of a second hybrid fin. The method further includes filling the first trench with a dielectric material disposed over the first hybrid fin and over the first part of the second hybrid fin. Thereafter, a second portion of the dummy gate is removed to form a second trench and the second trench is filled with a metal layer. The method further includes etching-back the metal layer, where a first plane defined by a first top surface of the metal layer is disposed beneath a second plane defined by a second top surface of a second part of the second hybrid fin after the etching-back the metal layer.

Abstract: An integrated circuit package including integrated circuit dies with slanted sidewalls and a method of forming are provided. The integrated circuit package may include a first integrated circuit die, a first gap-fill dielectric layer around the first integrated circuit die, a second integrated circuit die underneath the first integrated circuit die, and a second gap-fill dielectric layer around the second integrated circuit die. The first integrated circuit die may include a first substrate, wherein a first angle is between a first sidewall of the first substrate and a bottom surface of the first substrate, and a first interconnect structure on the bottom surface of the first substrate, wherein a second angle is between a first sidewall of the first interconnect structure and the bottom surface of the first substrate. The first angle may be larger than the second angle.

Abstract: A pseudo multi-port memory includes a memory array, a row decoder circuit, a timing controller circuit, a sense amplifier circuit, and a write driver circuit. The timing controller circuit outputs a timing control signal to the row decoder circuit, wherein during one memory clock cycle, the row decoder circuit is controlled by the timing control signal to make a read wordline (RWL) signal have an enable pulse and a write wordline (WWL) signal have multiple enable pulses. During one memory clock cycle, the sense amplifier circuit performs read operations upon a selected memory cell when the selected RWL is enabled by the enable pulse and the selected WWL is enabled by at least one first enable pulse, and the write driver circuit performs a write operation upon the selected memory cell when the selected WWL is enabled by one second enable pulse.

Abstract: A method for forming a semiconductor device is provided. The method includes forming a semiconductor protruding structure over a substrate and surrounding the semiconductor protruding structure with an insulating layer. The method also includes forming a dielectric layer over the insulating layer. The method further includes partially removing the dielectric layer and insulating layer using a planarization process. As a result, topmost surfaces of the semiconductor protruding structure, the insulating layer, and the dielectric layer are substantially level with each other. In addition, the method includes forming a protective layer to cover the topmost surfaces of the dielectric layer. The method includes recessing the insulating layer after the protective layer is formed such that the semiconductor protruding structure and a portion of the dielectric layer protrude from a top surface of a remaining portion of the insulating layer.

Abstract: A coated metal alloy substrate with at least one chamfered edge, a process for producing a coating a metal alloy substrate, and an electronic device having a housing comprising a coated metal alloy substrate are described. The coated metal alloy substrate with at least one chamfered edge comprises a hydrophobic anti-fingerprint layer deposited on the metal alloy substrate, a passivation layer deposited on the at least one chamfered edge, and a water based paint layer deposited on the passivation layer.

Abstract: A defect-reducing coating method is disclosed, which is characterized by making the coating surface of a sample face the bottom of the coating chamber, so that the sticking particles on side walls of the coating chamber will not fall on the coating surface of the sample during the coating process, thereby a smooth coating layer can be formed on the coating surface of the sample after the coating process is finished.

Abstract: Disclosed herein are compounds, compositions, and methods for inhibiting HECT E3 ubiquitin ligases. In some embodiments, the compounds are formulated as a pharmaceutical composition and administered to a subject in need thereof. In some embodiments, the subject in need thereof is diagnosed with a neurological disease or a cancer characterized by increased or ectopic HECT E3 ligase activity.

Abstract: The application discloses examples of a device housing of an electronic device including a magnesium-alloy substrate. The device housing further including a treatment layer applied over the magnesium-alloy substrate and a metallic coating layer applied over the treatment layer to provide a metallic luster. Further, a paint coating layer is disposed over a first portion of the metallic coating layer. Further, a top coating layer is applied over the paint coating layer and a visible second portion of the metallic coating layer.

Abstract: A method of manufacturing a semiconductor device includes forming a multi-layer stack of alternating first layers of a first semiconductor material and second layers of a second semiconductor material on a semiconductor substrate, forming a first recess through the multi-layer stack, and laterally recessing sidewalls of the second layers of the multi-layer stack. The sidewalls are adjacent to the first recess. The method further includes forming inner spacers with respective seams adjacent to the recessed second layers of the multi-layer stack and performing an anneal treatment on the inner spacers to close the respective seams.

Abstract: A method of manufacturing a carrying substrate is provided. At least one circuit component is disposed on a first circuit structure. An encapsulation layer is formed on the first circuit structure and encapsulates the circuit component. A second circuit structure is formed on the encapsulation layer and electrically connected to the circuit component. The circuit component is embedded in the encapsulation layer via an existing packaging process. Therefore, the routing area is increased, and a package substrate requiring a large size has a high yield and low manufacturing cost.

Abstract: An article includes a laminate material with an aerogel layer and a polysiloxane layer distinct from the aerogel layer and in contact with the aerogel layer either directly or through an adhesive that is in direct contact with both the aerogel layer and the polysiloxane layer; where the polysiloxane layer comprises a polysiloxane and greater than 5 weight-percent and 95 weight-percent or less based on polysiloxane layer weight of fire retarding additives selected from a group consisting of metal hydroxides, mixed metal hydroxides, hydrated metal salts, and any combinations thereof dispersed throughout the polysiloxane layer.

Abstract: A package structure and the manufacturing method thereof are provided. The package structure includes a first package including at least one first semiconductor die encapsulated in an insulating encapsulation and through insulator vias electrically connected to the at least one first semiconductor die, a second package including at least one second semiconductor die and conductive pads electrically connected to the at least one second semiconductor die, and solder joints located between the first package and the second package. The through insulator vias are encapsulated in the insulating encapsulation. The first package and the second package are electrically connected through the solder joints. A maximum size of the solder joints is greater than a maximum size of the through insulator vias measuring along a horizontal direction, and is greater than or substantially equal to a maximum size of the conductive pads measuring along the horizontal direction.

Abstract: Provided is an anti-fuse memory including a anti-fuse memory cell including an isolation structure, a select gate, first and second gate insulating layers, an anti-fuse gate, and first, second and third doped regions. The isolation structure is disposed in a substrate. The select gate is disposed on the substrate. The first gate insulating layer is disposed between the select gate and the substrate. The anti-fuse gate is disposed on the substrate and partially overlapped with the isolation structure. The second gate insulating layer is disposed between the anti-fuse gate and the substrate. The first doped region and the second doped region are disposed in the substrate at opposite sides of the select gate, respectively, wherein the first doped region is located between the select gate and the anti-fuse gate. The third doped region is disposed in the substrate and located between the first doped region and the isolation structure.

Abstract: Semiconductor devices and methods of manufacturing are presented in which inner spacers for nanostructures are manufactured. In embodiments a dielectric material is deposited for the inner spacer and then treated. The treatment may add material and cause an expansion in volume in order to close any seams that can interfere with subsequent processes.

Abstract: A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.

Abstract: The present disclosure is directed to positioning animated images within a dynamic keyboard interface. In particular, the methods and systems of the present disclosure can: receive, from a user device on which an application is executed, data indicating a context of: the application, and/or a dynamic keyboard interface provided in association with the application; identify, based at least in part on the data indicating the context, a plurality of different animated images, including an animated image comprising an advertisement, for presentation by the dynamic keyboard interface; communicate, to the user device, data indicating the plurality of different animated images; receive, from the user device, data indicating a selection of the animated image comprising the advertisement; and determine, based at least in part on the data indicating the selection and the data indicating the context, a position within the dynamic keyboard interface for presenting the animated image comprising the advertisement.

Abstract: A method of forming a semiconductor device includes forming a dummy gate structure across a fin protruding from a substrate, forming gate spacers on opposite sidewalls of the dummy gate structure, forming source/drain epitaxial structures on opposite sides of the dummy gate structure, forming a first interlayer dielectric (ILD) layer on the source/drain epitaxial structures and outer sidewalls of the gate spacers, replacing the dummy gate structure with a replacement gate structure, etching back the replacement gate structure to form a first recess between the gate spacers, forming a source/drain contact in the first ILD layer, and forming a second interlayer dielectric (ILD) layer to fill in the first recess between the gate spacers and over the source/drain contact.

Abstract: A device comprises a display that includes an aperture layer, a plurality of light sources, and a piezo material. The aperture layer includes a plurality of apertures. The plurality of light sources is arranged to correspond to the plurality of the aperture. The piezo material is coupled to the light sources and is configured to alter a distance between the light sources and the corresponding apertures.

Abstract: A nozzle is provided and includes a carrying segment, an assembling segment, a conical frustum segment, and at least one ring-shaped rib formed on the carrying segment and surrounding the conical frustum segment. The carrying segment has a top side and an opposite bottom side. The assembling segment is formed by extending from the bottom side of the carrying segment. The conical frustum segment is formed to taper from the top side of the carrying segment in a direction away from the assembling segment. The conical frustum segment defines a central axis, and a surrounding lateral surface of the conical frustum segment and a plane perpendicular to the central axis have an angle therebetween that is within a range from 35 degrees to 70 degrees. The conical frustum segment, the carrying segment, and the assembling segment jointly define an airflow channel penetrating therethrough along the central axis.