Patents by Inventor Chi-Hao Chiu

Chi-Hao Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8390991
    Abstract: A stacked solid state solid electrolytic capacitor includes a plurality of capacitor units, a substrate unit and a package unit. The substrate unit includes a positive guiding substrate and a negative guiding substrate. The positive guiding substrate has a positive exposed end integrally extended therefrom along a first predetermined direction. The negative guiding substrate has a first negative exposed end integrally extended therefrom along a second predetermined direction, a second negative exposed end integrally extended therefrom along a third predetermined direction, and a third negative exposed end integrally extended therefrom along a fourth predetermined direction. The first, the second, the third and the fourth predetermined directions are different. The capacitor units are stacked on top of one another and disposed on the negative guiding substrate. The package unit encloses the capacitor units, one part of the positive and one part of the negative guiding substrate.
    Type: Grant
    Filed: July 9, 2010
    Date of Patent: March 5, 2013
    Assignee: Apaq Technology Co., Ltd.
    Inventors: Chi-Hao Chiu, Yui-Shin Fran, Ching-Feng Lin, Chun-Chia Huang, Chun-Hung Lin, Wen-Yen Huang
  • Patent number: 8373972
    Abstract: A solid electrolytic capacitor with a protective structure, which includes stacked capacitor elements electrically connected to the positive and negative terminal. A packaging material such as synthetic resin is used to encapsulate the capacitor elements, the positive terminal, and the negative terminal. Before packaging, a protective layer is formed by a colloid material, which covers the main body of the capacitor that includes the capacitor elements, the positive terminal, and the negative terminal. The protective layer provides a better seal and relieves the external pressure exerting on the capacitor during the packaging process. The protection prevents structural damage to the capacitor's main body while reducing the risk of short-circuits and excessive current leakage.
    Type: Grant
    Filed: October 20, 2010
    Date of Patent: February 12, 2013
    Assignee: Apaq Technology Co., Ltd.
    Inventors: Ching-Feng Lin, Chi-Hao Chiu, Wen-Yen Huang, Chun-Chia Huang
  • Patent number: 8369066
    Abstract: A lamellar stacked solid electrolytic capacitor includes a plurality of capacitor units, a substrate unit and a package unit. Each capacitor unit is composed of a negative foil, an isolation paper with conductive polymer substance, a positive foil, an isolation paper with conductive polymer substance and a negative foil that are stacked onto each other in sequence, the positive foils of the capacitor units are electrically connected to each other, the negative foils of the capacitor units are electrically connected to each other, and the positive foils and the negative foils are insulated from each other. The substrate unit has a positive guiding substrate electrically connected to the positive foils of the capacitor units and a negative guiding substrate electrically connected to the negative foils of the capacitor units. The package unit covers the capacitor units and one part of the substrate unit.
    Type: Grant
    Filed: February 26, 2010
    Date of Patent: February 5, 2013
    Assignee: Apaq Technology Co., Ltd.
    Inventors: Ching-Feng Lin, Yui-Hsin Fran, Chi-Hao Chiu, Ming-Tsung Chen, Cheng-Wei Lai, Chun-Chia Huang
  • Publication number: 20130010404
    Abstract: A capacitance unit includes an anode portion, an insulating portion, a cathode portion and a colloid portion. The front end of the anode portion extends to from an anode terminal. The insulating portion surrounds the anode portion and covers a first partial surface of the anode portion. The cathode portion is disposed next to the insulating portion, and the cathode portion covers a second partial surface of the anode portion. The colloid portion is disposed next to the insulating portion, and the colloid portion surrounds the cathode portion and covers a partial surface of the cathode portion.
    Type: Application
    Filed: July 7, 2011
    Publication date: January 10, 2013
    Applicant: APAQ TECHNOLOGY CO., LTD.
    Inventors: CHI-HAO CHIU, CHING-FENG LIN, KUN-HUANG CHANG
  • Patent number: 8310814
    Abstract: A stacked capacitor with positive multi-pin structure includes a plurality of capacitor units, a substrate unit and a package unit. Each capacitor unit has a positive electrode that has a positive pin extended outwards therefrom. The positive pins of the capacitor units are divided into a plurality of positive pin units that are separated from each other, and the positive pins of each positive pin unit are electrically stacked onto each other. Each capacitor unit has a negative electrode, and the negative electrodes of the capacitor units are electrically stacked onto each other. The substrate unit has a positive guiding substrate electrically connected to the positive pins of the capacitor units and a negative guiding substrate electrically connected to the negative electrodes of the capacitor units. The package unit covers the capacitor units and one part of the substrate unit.
    Type: Grant
    Filed: October 7, 2009
    Date of Patent: November 13, 2012
    Assignee: Apaq Technology Co., Ltd.
    Inventors: Chi-Hao Chiu, Yui-Hsin Fran, Ching-Feng Lin, Chun-Chia Huang
  • Patent number: 8305734
    Abstract: An insulating encapsulation structure is applied to a chip type solid electrolytic capacitor that includes an aluminum metallic body having an aluminum core layer. An upper oxide film and a lower oxide film respectively having fine holes on their surfaces are respectively formed on the top and the bottom of the aluminum core layer. On side surfaces of the metallic body is a plurality of cut burrs. The upper oxide film and the lower oxide film of the metallic body are respectively separated by a separating layer to form an anode and a cathode. The insulating encapsulation structure includes an insulating cover layer enclosing an outer surface of the metallic body to cover the cut burrs. Thereby, the required chemical conversion process is reduced along with current leakage, the overall manufacturing cost is lowered, and the mechanical strength for the edge of the metallic body is reinforced.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: November 6, 2012
    Assignee: Apaq Technology Co., Ltd.
    Inventors: Chi-Hao Chiu, Ming-Tsung Chen, Chiao-Yinms Yang
  • Patent number: 8305735
    Abstract: A stacked solid electrolytic capacitor with positive multi-pin structure includes a plurality of capacitor units, a substrate unit and a package unit. The positive electrode of each capacitor unit has a positive pin extended outwards therefrom. The positive pins are divided into a plurality of positive pin units that are separated from each other and electrically stacked onto each other. The negative electrode of each capacitor unit has a negative pin extended outwards therefrom. The negative pins are divided into a plurality of negative pin units. The negative pin units are separated from each other and the negative pins of each negative pin unit are electrically stacked onto each other. The substrate unit has a positive guiding substrate electrically connected to the positive pins and a negative guiding substrate electrically connected to the negative pins. The package unit covers the capacitor units and one part of the substrate unit.
    Type: Grant
    Filed: November 30, 2009
    Date of Patent: November 6, 2012
    Assignee: Apaq Technology Co., Ltd.
    Inventors: Yui-Shin Fran, Ching-Feng Lin, Chi-Hao Chiu, Chun-Chia Huang, Wen-Yen Huang
  • Publication number: 20120099247
    Abstract: A solid electrolytic capacitor with a protective structure, which includes stacked capacitor elements electrically connected to the positive and negative terminal. A packaging material such as synthetic resin is used to encapsulate the capacitor elements, the positive terminal, and the negative terminal. Before packaging, a protective layer is formed by a colloid material, which covers the main body of the capacitor that includes the capacitor elements, the positive terminal, and the negative terminal. The protective layer provides a better seal and relieves the external pressure exerting on the capacitor during the packaging process. The protection prevents structural damage to the capacitor's main body while reducing the risk of short-circuits and excessive current leakage.
    Type: Application
    Filed: October 20, 2010
    Publication date: April 26, 2012
    Applicant: APAQ TECHNOLOGY CO., LTD.
    Inventors: CHING-FENG LIN, CHI-HAO CHIU, WEN-YEN HUANG, CHUN-CHIA HUANG
  • Patent number: 8164883
    Abstract: A stacked solid electrolytic capacitor and a method for manufacturing the same are disclosed. The stacked solid electrolytic capacitor includes two capacitor sets, a positive electrode conducting device, a negative electrode conducting device, and a package unit. Each capacitor set includes at least one capacitor unit. The front side of the positive electrode portion of the capacitor set extends to form a positive electrode pin. The positive electrode conducting device has at least one first positive electrode conducting lead frame and at least one second positive electrode conducting lead frame. The first positive electrode conducting lead frame is electrically connected with the second positive electrode conducting lead frame. The negative electrode conducting device has at least one negative electrode conducting lead frame, and is electrically connected with the negative electrode of the two capacitor sets by using metal conductive material.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: April 24, 2012
    Assignee: Apaq Technology Co., Ltd.
    Inventors: Chi-Hao Chiu, Ching-Feng Lin, Chun-Chia Huang, Chien-Ting Liu
  • Publication number: 20120092810
    Abstract: An insulating encapsulation structure is applied to a chip type solid electrolytic capacitor that includes an aluminum metallic body having an aluminum core layer. An upper oxide film and a lower oxide film respectively having fine holes on their surfaces are respectively formed on the top and the bottom of the aluminum core layer. On side surfaces of the metallic body is a plurality of cut burrs. The upper oxide film and the lower oxide film of the metallic body are respectively separated by a separating layer to form an anode and a cathode. The insulating encapsulation structure includes an insulating cover layer enclosing an outer surface of the metallic body to cover the cut burrs. Thereby, the required chemical conversion process is reduced along with current leakage, the overall manufacturing cost is lowered, and the mechanical strength for the edge of the metallic body is reinforced.
    Type: Application
    Filed: October 19, 2010
    Publication date: April 19, 2012
    Applicant: APAQ TECHNOLOGY CO., LTD.
    Inventors: CHI-HAO CHIU, MING-TSUNG CHEN, CHIAO-YINMS YANG
  • Publication number: 20110216475
    Abstract: A stacked solid-state electrolytic capacitor with multi-directional product lead frame structure includes a plurality of capacitor units, a substrate unit and a package unit. The capacitor units are stacked onto each other. Each capacitor unit has a positive electrode and a negative electrode, the positive electrode of each capacitor unit has a positive pin extended outwards, the positive pins are electrically stacked onto each other, and the negative electrodes are electrically stacked onto each other. The substrate unit has at least one positive guiding substrate electrically connected to the positive pins of the capacitor units and a plurality of negative guiding substrates electrically connected to the negative electrodes of the capacitor units. The package unit covers the capacitor units and one part of the substrate unit in order to expose an end of the at least one positive guiding substrate and an end of each negative guiding substrate.
    Type: Application
    Filed: July 9, 2010
    Publication date: September 8, 2011
    Applicant: APAQ TECHNOLOGY CO., LTD.
    Inventors: Chi-Hao Chiu, Yui-Shin Fran, Ching-Feng Lin, Chun-Chia Huang, Chun-Hung Lin, Wen-Yen Huang
  • Publication number: 20110122544
    Abstract: A stacked solid electrolytic capacitor and a method for manufacturing the same are disclosed. The stacked solid electrolytic capacitor includes two capacitor sets, a positive electrode conducting device, a negative electrode conducting device, and a package unit. Each capacitor set includes at least one capacitor unit. The front side of the positive electrode portion of the capacitor set extends to form a positive electrode pin. The positive electrode conducting device has at least one first positive electrode conducting lead frame and at least one second positive electrode conducting lead frame. The first positive electrode conducting lead frame is electrically connected with the second positive electrode conducting lead frame. The negative electrode conducting device has at least one negative electrode conducting lead frame, and is electrically connected with the negative electrode of the two capacitor sets by using metal conductive material.
    Type: Application
    Filed: June 11, 2010
    Publication date: May 26, 2011
    Inventors: Chi-Hao CHIU, Ching-Feng Lin, Chun-Chia Huang, Chien-Ting Liu
  • Publication number: 20110007452
    Abstract: A lamellar stacked solid electrolytic capacitor includes a plurality of capacitor units, a substrate unit and a package unit. Each capacitor unit is composed of a negative foil, an isolation paper with conductive polymer substance, a positive foil, an isolation paper with conductive polymer substance and a negative foil that are stacked onto each other in sequence, the positive foils of the capacitor units are electrically connected to each other, the negative foils of the capacitor units are electrically connected to each other, and the positive foils and the negative foils are insulated from each other. The substrate unit has a positive guiding substrate electrically connected to the positive foils of the capacitor units and a negative guiding substrate electrically connected to the negative foils of the capacitor units. The package unit covers the capacitor units and one part of the substrate unit.
    Type: Application
    Filed: February 26, 2010
    Publication date: January 13, 2011
    Applicant: APAQ TECHNOLOGY CO., LTD.
    Inventors: Ching-Feng Lin, Yui-Hsin Fran, Chi-Hao Chiu, Ming-Tsung Chen, Cheng-Wei Lai, Chun-Chia Huang
  • Publication number: 20110007451
    Abstract: A stacked solid electrolytic capacitor with positive multi-pin structure includes a plurality of capacitor units, a substrate unit and a package unit. The positive electrode of each capacitor unit has a positive pin extended outwards therefrom. The positive pins are divided into a plurality of positive pin units that are separated from each other and electrically stacked onto each other. The negative electrode of each capacitor unit has a negative pin extended outwards therefrom. The negative pins are divided into a plurality of negative pin units. The negative pin units are separated from each other and the negative pins of each negative pin unit are electrically stacked onto each other. The substrate unit has a positive guiding substrate electrically connected to the positive pins and a negative guiding substrate electrically connected to the negative pins. The package unit covers the capacitor units and one part of the substrate unit.
    Type: Application
    Filed: November 30, 2009
    Publication date: January 13, 2011
    Applicant: APAQ TECHNOLOGY CO., LTD.
    Inventors: Yui-Shin Fran, Ching-Feng Lin, Chi-Hao Chiu, Chun-Chia Huang, Wen-Yen Huang
  • Publication number: 20110002087
    Abstract: A stacked capacitor with positive multi-pin structure includes a plurality of capacitor units, a substrate unit and a package unit. Each capacitor unit has a positive electrode that has a positive pin extended outwards therefrom. The positive pins of the capacitor units are divided into a plurality of positive pin units that are separated from each other, and the positive pins of each positive pin unit are electrically stacked onto each other. Each capacitor unit has a negative electrode, and the negative electrodes of the capacitor units are electrically stacked onto each other. The substrate unit has a positive guiding substrate electrically connected to the positive pins of the capacitor units and a negative guiding substrate electrically connected to the negative electrodes of the capacitor units. The package unit covers the capacitor units and one part of the substrate unit.
    Type: Application
    Filed: October 7, 2009
    Publication date: January 6, 2011
    Inventors: Chi-Hao Chiu, Yui-Hsin Fran, Ching-Feng Lin, Chun-Chia Huang
  • Patent number: 7404663
    Abstract: A backlight module is suitable for use in a liquid crystal display. The backlight module includes a back plate, and a lamp, over the back plate by a distance. The back plate has a hole under the lamp. The hole can be a hole under the lamp corresponding to an electrode of a high voltage end of the lamp. The hole or a certain number of the holes can be replaced by an indentation, which can also effectively increase the separation distance between the lamp and the back plate. Actually, the hole and the indentation can be used together to form a desired pattern corresponding to the lamp. The lamp can be a plurality of lamp.
    Type: Grant
    Filed: April 8, 2005
    Date of Patent: July 29, 2008
    Assignee: Hannstar Display Corporation
    Inventors: Chi-Hao Chiu, Ping-Fu Wang
  • Patent number: 7253508
    Abstract: A semiconductor package includes a flip chip mounted on a plurality of leads and encapsulated by a molding compound. The upper surfaces of the leads includes a plurality of bump-bonding regions at the fan-in ends of the leads, and the lower surfaces of the leads include a plurality of outer connecting regions at the fan-out ends of the leads. A plurality of indentations are formed at the upper surfaces of the leads and adjacent to the corresponding bump-bonding regions so as to avoid solder contamination on the leads. After molding, the indentations are filled with the molding compound. Preferably, the indentations have a reversed “?”-shaped profile to prevent bumps of the flip chip from excessively wetting over the other portions of the leads to firmly fix the fan-in ends of the leads.
    Type: Grant
    Filed: December 17, 2004
    Date of Patent: August 7, 2007
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chien Liu, Hsueh-Te Wang, Meng-Jen Wang, Chi-Hao Chiu, Tai-Yuan Huang
  • Publication number: 20070085218
    Abstract: A flip chip package structure is provided. A chip is electrically connected to a substrate. A heat sink is attached to the backside of the chip. The heat sink has at least a through hole located at a peripheral region and laterally adjacent to the chip. A dispensing process is carried out to deliver an underfill material via the through hole such that the space between the chip and the substrate is filled. The underfill material also extends to cover a portion of the heat sink so that the heat sink and the substrate are connected together. The underfill material is cured to fix the heat sink, the substrate and the chip in position.
    Type: Application
    Filed: November 24, 2006
    Publication date: April 19, 2007
    Applicant: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Yu-Wen Chen, Chih-Ming Chung, Chi-Hao Chiu
  • Patent number: 7164202
    Abstract: A quad flat flip chip package and a leadframe therefor are provided. A bump connection part is defined by bending or etching the leads of the leadframe. Thus, the bump formed after a reflow process is limited within the bump connection part, and the collapse of the bump can be prevented. Moreover, and the manufacturing costs of the package can be decreased and the process thereof can be simplified.
    Type: Grant
    Filed: November 15, 2004
    Date of Patent: January 16, 2007
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Hsueh-Te Wang, Meng-Jen Wang, Chien Liu, Chi-Hao Chiu
  • Patent number: 7163840
    Abstract: A flip chip package structure and manufacturing method thereof is provided. A chip is electrically connected to a substrate. A heat sink is attached to the backside of the chip. The heat sink has at least a through hole located at a peripheral region and laterally adjacent to the chip. A dispensing process is carried out to deliver an underfill material via the through hole such that the space between the chip and the substrate is filled. The underfill material also extends to cover a portion of the heat sink so that the heat sink and the substrate are connected together. The underfill material is cured to fix the heat sink, the substrate and the chip in position.
    Type: Grant
    Filed: May 17, 2004
    Date of Patent: January 16, 2007
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Yu-Wen Chen, Chih-Ming Chung, Chi-Hao Chiu