Patents by Inventor Chi-Hsiang Chang
Chi-Hsiang Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128364Abstract: A semiconductor device includes a fin structure, a metal gate stack, a barrier structure and an epitaxial source/drain region. The fin structure is over a substrate. The metal gate stack is across the fin structure. The barrier structure is on opposite sides of the metal gate stack. The barrier structure comprises one or more passivation layers and one or more barrier layers, and the one or more passivation layers have a material different from a material of the one or more barrier layers. The epitaxial source/drain region is over the barrier structure.Type: ApplicationFiled: March 27, 2023Publication date: April 18, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chun-Ming LUNG, Chung-Ting KO, Ting-Hsiang CHANG, Sung-En LIN, Chi On CHUI
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Patent number: 11942652Abstract: The disclosure provides a limit device and a robot using the same. The limit device comprises a first connecting member, a transmission rod and a second connecting member. The first connecting member comprising a first main body portion and two first connecting elements. The two first connecting elements are arranged at intervals. The two first connecting elements are respectively connected to the first main body. The transmission rod comprising a first end and a second end. The first end and the second end are arranged at intervals. The first end penetrates through one of the two first connecting elements. The second end penetrates through the other one of the two first connecting element. The second connecting member provided with two indexing buckles. The two indexing buckles are arranged at intervals, each of the indexing buckles comprises a first limiting groove and a second limiting groove.Type: GrantFiled: April 13, 2022Date of Patent: March 26, 2024Assignees: Futaijing Precision Electronics (Yantai) Co., Ltd., HON HAI PRECISION INDUSTRY CO., LTD.Inventors: Chen-Ting Kao, Chi-Cheng Wen, Yu-Sheng Chang, Chih-Cheng Lee, Chiung-Hsiang Wu, Sheng-Li Yen, Yu-Cheng Zhang, Chang-Ju Hsieh, Chen Chao
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Publication number: 20240096800Abstract: A semiconductor device includes first and second active regions extending in parallel in a substrate, a plurality of conductive patterns, each conductive pattern of the plurality of conductive patterns extending on the substrate across each of the first and second active regions, and a plurality of metal lines, each metal line of the plurality of metal lines overlying and extending across each of the first and second active regions. Each conductive pattern of the plurality of conductive patterns is electrically connected in parallel with each metal line of the plurality of metal lines.Type: ApplicationFiled: November 27, 2023Publication date: March 21, 2024Inventors: Fei Fan DUAN, Fong-yuan CHANG, Chi-Yu LU, Po-Hsiang HUANG, Chih-Liang CHEN
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Patent number: 11929016Abstract: A scan-type display apparatus includes an LED array and a scan driver. The LED array has a common anode configuration, and includes multiple scan lines, multiple data lines and multiple LEDs. The scan driver includes multiple scan driving circuits. Each scan driving circuit includes a voltage generator and a detector. The voltage generator has an output terminal that is connected to the scan line corresponding to the scan driving circuit, and is configured to output one of an input voltage and a clamp voltage at the output terminal of the voltage generator. The detector is connected to the output terminal of the voltage generator, and generates a detection signal that indicates whether any one of the LEDs connected to the scan line corresponding to the scan driving circuit is short circuited based on a voltage at the output terminal of the voltage generator and a detection timing signal.Type: GrantFiled: December 5, 2022Date of Patent: March 12, 2024Assignee: MACROBLOCK, INC.Inventors: Chi-Min Hsieh, Che-Wei Chang, Chen-Yuan Kuo, Wei-Hsiang Cheng
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Publication number: 20240079315Abstract: Improved control of via anchor profiles in metals at a contact layer can be achieved by slowing down an anchor etching process and by introducing a passivation operation. By first passivating a metallic surface, etchants can be prevented from dispersing along grain boundaries, thereby distorting the shape of the via anchor. An iterative scheme that involves multiple cycles of alternating passivation and etching operations can control the formation of optimal via anchor profiles. When a desirable anchor shape is achieved, the anchor maintains structural integrity of the vias, thereby improving reliability of the interconnect structure.Type: ApplicationFiled: September 1, 2022Publication date: March 7, 2024Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Shin WANG, Yu-Hsiang Wang, Wei-Ting Chang, Fan-Yi Hsu
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Publication number: 20230231038Abstract: A method includes forming a first fin and a second fin over a substrate. The method includes forming a first dummy gate structure that straddles the first fin and the second fin. The first dummy gate structure includes a first dummy gate dielectric and a first dummy gate disposed over the first dummy gate dielectric. The method includes replacing a portion of the first dummy gate with a gate isolation structure. The portion of the first dummy gate is disposed over the second fin. The method includes removing the first dummy gate. The method includes removing a first portion of the first dummy gate dielectric around the first fin, while leaving a second portion of the first dummy gate dielectric around the second fin intact. The method includes forming a gate feature straddling the first fin and the second fin, wherein the gate isolation structure intersects the gate feature.Type: ApplicationFiled: March 23, 2023Publication date: July 20, 2023Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Shih-Yao Lin, Chih-Han Lin, Shu-Uei Jang, Ya-Yi Tsai, Chi-Hsiang Chang, Tzu-Chung Wang, Shu-Yuan Ku
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Publication number: 20230187542Abstract: A semiconductor device and method of fabricating a semiconductor device involves formation of a trench above a fin (e.g. a fin of a FinFET device) of the semiconductor device and formation of a multi-layer dielectric structure within the trench. The profile of the multi-layer dielectric structure can be controlled depending on the application to reduce shadowing effects and reduce cut failure risk, among other possible benefits. The multi-layer dielectric structure can include two layers, three layers, or any number of layers and can have a stepped profile, a linear profile, or any other type of profile.Type: ApplicationFiled: February 9, 2023Publication date: June 15, 2023Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Ya-Yi Tsai, Chi-Hsiang Chang, Shih-Yao LIN, Tzu-Chung Wang, Shu-Yuan Ku
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Patent number: 11626510Abstract: A method includes forming a first fin and a second fin over a substrate. The method includes forming a first dummy gate structure that straddles the first fin and the second fin. The first dummy gate structure includes a first dummy gate dielectric and a first dummy gate disposed over the first dummy gate dielectric. The method includes replacing a portion of the first dummy gate with a gate isolation structure. The portion of the first dummy gate is disposed over the second fin. The method includes removing the first dummy gate. The method includes removing a first portion of the first dummy gate dielectric around the first fin, while leaving a second portion of the first dummy gate dielectric around the second fin intact. The method includes forming a gate feature straddling the first fin and the second fin, wherein the gate isolation structure intersects the gate feature.Type: GrantFiled: January 24, 2022Date of Patent: April 11, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Shih-Yao Lin, Chih-Han Lin, Shu-Uei Jang, Ya-Yi Tsai, Chi-Hsiang Chang, Tzu-Chung Wang, Shu-Yuan Ku
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Patent number: 11600718Abstract: A semiconductor device and method of fabricating a semiconductor device involves formation of a trench above a fin (e.g. a fin of a FinFET device) of the semiconductor device and formation of a multi-layer dielectric structure within the trench. The profile of the multi-layer dielectric structure can be controlled depending on the application to reduce shadowing effects and reduce cut failure risk, among other possible benefits. The multi-layer dielectric structure can include two layers, three layers, or any number of layers and can have a stepped profile, a linear profile, or any other type of profile.Type: GrantFiled: April 22, 2021Date of Patent: March 7, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Ya-Yi Tsai, Chi-Hsiang Chang, Shih-Yao Lin, Tzu-Chung Wang, Shu-Yuan Ku
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Publication number: 20230061323Abstract: A method of fabricating a semiconductor device is described. A substrate is provided. A plurality of fins is formed extending from the substrate, the fins including a first group of active fins arranged in an active region, and including an inactive fin having at least a portion in an inactive region, the active fins separated by first trench regions between adjacent of the active regions, the inactive fin separated from its closest active fin by a second trench region, the second trench region having a greater width than that of a trench region of the first trench regions. A dummy fin is formed on the isolation dielectric in the second trench region, the dummy fin disposed between the first group of active fins and the inactive fin. A dummy gate is formed over the fins. The gate isolation structure is disposed between the dummy fin and the inactive fin and separates regions of the dummy gate.Type: ApplicationFiled: August 28, 2021Publication date: March 2, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Ya-Yi Tsai, Shih-Yao Lin, Chi-Hsiang Chang, Wei-Han Chen, Shu-Yuan Ku
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Publication number: 20220344491Abstract: A semiconductor device and method of fabricating a semiconductor device involves formation of a trench above a fin (e.g. a fin of a FinFET device) of the semiconductor device and formation of a multi-layer dielectric structure within the trench. The profile of the multi-layer dielectric structure can be controlled depending on the application to reduce shadowing effects and reduce cut failure risk, among other possible benefits. The multi-layer dielectric structure can include two layers, three layers, or any number of layers and can have a stepped profile, a linear profile, or any other type of profile.Type: ApplicationFiled: April 22, 2021Publication date: October 27, 2022Applicant: Taiwan Semiconductor Manufacturing Company LimitedInventors: Ya-Yi Tsai, Chi-Hsiang Chang, Shih-Yao LIN, Tzu-Chung Wang, Shu-Yuan Ku
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Publication number: 20220149181Abstract: A method includes forming a first fin and a second fin over a substrate. The method includes forming a first dummy gate structure that straddles the first fin and the second fin. The first dummy gate structure includes a first dummy gate dielectric and a first dummy gate disposed over the first dummy gate dielectric. The method includes replacing a portion of the first dummy gate with a gate isolation structure. The portion of the first dummy gate is disposed over the second fin. The method includes removing the first dummy gate. The method includes removing a first portion of the first dummy gate dielectric around the first fin, while leaving a second portion of the first dummy gate dielectric around the second fin intact. The method includes forming a gate feature straddling the first fin and the second fin, wherein the gate isolation structure intersects the gate feature.Type: ApplicationFiled: January 24, 2022Publication date: May 12, 2022Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Shih-Yao Lin, Chih-Han Lin, Shu-Uei Jang, Ya-Yi Tsai, Chi-Hsiang Chang, Tzu-Chung Wang, Shu-Yuan Ku
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Patent number: 11233139Abstract: A method includes forming a first fin and a second fin over a substrate. The method includes forming a first dummy gate structure that straddles the first fin and the second fin. The first dummy gate structure includes a first dummy gate dielectric and a first dummy gate disposed over the first dummy gate dielectric. The method includes replacing a portion of the first dummy gate with a gate isolation structure. The portion of the first dummy gate is disposed over the second fin. The method includes removing the first dummy gate. The method includes removing a first portion of the first dummy gate dielectric around the first fin, while leaving a second portion of the first dummy gate dielectric around the second fin intact. The method includes forming a gate feature straddling the first fin and the second fin, wherein the gate isolation structure intersects the gate feature.Type: GrantFiled: June 26, 2020Date of Patent: January 25, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Shih-Yao Lin, Chih-Han Lin, Shu-Yuan Ku, Tzu-Chung Wang, Shu-Uei Jang, Ya-Yi Tsai, Chi-Hsiang Chang
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Publication number: 20210408263Abstract: A method includes forming a first fin and a second fin over a substrate. The method includes forming a first dummy gate structure that straddles the first fin and the second fin. The first dummy gate structure includes a first dummy gate dielectric and a first dummy gate disposed over the first dummy gate dielectric. The method includes replacing a portion of the first dummy gate with a gate isolation structure. The portion of the first dummy gate is disposed over the second fin. The method includes removing the first dummy gate. The method includes removing a first portion of the first dummy gate dielectric around the first fin, while leaving a second portion of the first dummy gate dielectric around the second fin intact. The method includes forming a gate feature straddling the first fin and the second fin, wherein the gate isolation structure intersects the gate feature.Type: ApplicationFiled: June 26, 2020Publication date: December 30, 2021Inventors: Shih-Yao Lin, Chih-Han Lin, Shu-Yuan Ku, Tzu-Chung Wang, Shu-Uei Jang, Ya-Yi Tsai, Chi-Hsiang Chang
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Publication number: 20140115622Abstract: An interactive video/image-relevant information embedding technology contains: a server side including a user client-server operation interface module for interacting with the client side; a video/image database for saving videos/images; a label database for saving external information; a video/image content analysis module for segmenting, tracking, recognizing specified items in the videos/images; an external-information retrieval engine for retrieving external information from the public search engine, label database, or additional database; a video/image-external information relation analysis module for creating on-the-fly labels for the specified items in videos/images; a client side which includes: a client-server operation interface module for interacting with the server side; a user operation interface module for interacting with the user/label creator; an original video/image database for saving videos/images; a label information database for saving external information; a video/image content analysisType: ApplicationFiled: October 18, 2012Publication date: April 24, 2014Inventors: Chi-Hsiang Chang, Wei-Yao Lin
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Publication number: 20130270120Abstract: A system and process for reducing cosmetic defects such as black lines, and otherwise improving the final cosmetic appearance of anodized parts is disclosed. The process can include degreasing an aluminum or other metal part in a neutral to low alkaline solution having a mild detergent, chemically polishing the metal part with a specialized solution having one or more additives at an increased temperature for a reduced amount of time, and anodizing the metal part at a reduced voltage and for a reduced amount of time. An activating step can also be performed as part of the overall process. Tap water rinse, deionized water rinse, desmut, seal and bake procedures can also be performed on the metal part.Type: ApplicationFiled: June 24, 2011Publication date: October 17, 2013Applicant: Apple Inc.Inventors: Zhicong Yao, Chi-Hsiang Chang
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Patent number: 8169043Abstract: An optical sensor package structure includes a substrate, a metal plate, an optical sensing chip, a plurality of bonding wires and a lens module. The substrate includes a top surface, a bottom surface and a hole penetrating the top surface and the bottom surface. The metal plate covers the hole from the bottom surface of the substrate. The optical sensing chip is received in the hole and mounted on the metal plate. The bonding wires interconnect the optical sensing chip and the top surface of substrate. The lens module is covering on the hole and mounting on the top surface of the substrate to enclose the optical sensing chip and the bonding wires. Because the optical sensing chip is received in the hole of the substrate, the height of the optical sensor package structure can be reduced to adapt to a compact size electrical device.Type: GrantFiled: February 9, 2010Date of Patent: May 1, 2012Assignee: Cheng Uei Precision Industry Co., Ltd.Inventors: Yu-Hsiang Chen, Cheng-I Lu, Min-Nan Yeh, Chi-Hsiang Chang
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Publication number: 20110175182Abstract: An optical sensor package structure includes a substrate, a metal plate, an optical sensing chip, a plurality of bonding wires and a lens module. The substrate includes a top surface, a bottom surface and a hole penetrating the top surface and the bottom surface. The metal plate covers the hole from the bottom surface of the substrate. The optical sensing chip is received in the hole and mounted on the metal plate. The bonding wires interconnect the optical sensing chip and the top surface of substrate. The lens module is covering on the hole and mounting on the top surface of the substrate to enclose the optical sensing chip and the bonding wires. Because the optical sensing chip is received in the hole of the substrate, the height of the optical sensor package structure can be reduced to adapt to a compact size electrical device.Type: ApplicationFiled: February 9, 2010Publication date: July 21, 2011Inventors: Yu-Hsiang Chen, Cheng-I Lu, Min-Nan Yeh, Chi-Hsiang Chang
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Patent number: 7486601Abstract: Method and related apparatus for generating fixed packets while writing data into CDs. The present invention records a total-block number of a write-in data with a counter, and a waiting-coding number with another counter, so as to generate fixed packets efficiently and correctly, and prevent buffer under run when writing the write-in data to the CD.Type: GrantFiled: November 27, 2006Date of Patent: February 3, 2009Assignee: MediaTek Inc.Inventors: Chi-Hsiang Chang, Jenn-Ning Yang
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Patent number: 7418607Abstract: The present invention relates to an automatic power conservation method for an optical media device, which is capable of turning off other circuit components that are still in operation using the host interface of the optical media device when the optical media device enters the sleep-mode, and the host interface also being used to respond to an external signal of the optical media device; using the host interface to wake up those circuit components if the external input signal of the optical media device requesting the optical media device to exit the sleep-mode.Type: GrantFiled: March 31, 2004Date of Patent: August 26, 2008Assignee: ALi CorporationInventors: Ya-Fang Nien, Kuo-An Chang, Chi-Hsiang Chang