Abstract: A trench gate MOSFET is provided. An epitaxial layer is disposed on a substrate. A body layer is disposed in the epitaxial layer. The epitaxial layer has a first trench therein, the body layer has a second trench therein, and the first trench is disposed below the second trench. A first insulating layer is disposed on a surface of the first trench. A second insulating layer is disposed in the first trench. A first conductive layer is disposed between the first and second insulating layers. A second conductive layer is disposed in the second trench. A third insulating layer is disposed between the second conductive layer and the body layer and between the second conductive layer and the first conductive layer. A dielectric layer is disposed on the epitaxial layer and covers the second conductive layer. Two doped regions are disposed in the body layer respectively beside the second trench.

Abstract: A trench gate MOSFET is provided. An epitaxial layer is disposed on a substrate. A body layer is disposed in the epitaxial layer. The epitaxial layer has a first trench therein, the body layer has a second trench therein, and the first trench is disposed below the second trench. A first conductive layer is disposed in the first trench. A first insulating layer is disposed between the first conductive layer and the epitaxial layer. A second conductive layer is disposed on a sidewall of the second trench. A second insulating layer is disposed between the second conductive layer and the body layer, and between the second conductive layer and the first conductive layer. A dielectric layer is disposed on the epitaxial layer and fills up the second trench. Two doped regions are disposed in the body layer respectively beside the second trench.

Abstract: A method of forming a trench gate MOSFET is provided. An epitaxial layer is formed on a substrate. A trench is formed in the epitaxial layer. A first insulating layer is conformally formed on surfaces of the epitaxial layer and the trench. A first conductive layer is formed at the bottom of the trench. A portion of the first insulating layer is removed to form a second insulating layer exposing an upper portion of the first conductive layer. An oxidation process is performed to oxidize the first conductive layer to a third insulating layer, wherein a fourth insulating layer is simultaneously formed on the surface of the epitaxial layer and on the sidewall of the trench. A second conductive layer is formed in the trench. Two body layers are formed in the epitaxial layer beside the trench. Two doped regions are formed in the body layers respectively beside the trench.

Abstract: A method of forming a trench gate MOSFET is provided. An epitaxial layer is formed on a substrate. A trench is formed in the epitaxial layer. A first insulating layer is conformally formed on surfaces of the epitaxial layer and the trench. A first conductive layer is formed at the bottom of the trench. A portion of the first insulating layer is removed to form a second insulating layer exposing an upper portion of the first conductive layer. An oxidation process is performed to oxidize the first conductive layer to a third insulating layer, wherein a fourth insulating layer is simultaneously formed on the surface of the epitaxial layer and on the sidewall of the trench. A second conductive layer is formed in the trench. Two body layers are formed in the epitaxial layer beside the trench. Two doped regions are formed in the body layers respectively beside the trench.

Abstract: A trench gate MOSFET is provided. An epitaxial layer is disposed on a substrate. A body layer is disposed in the epitaxial layer. The epitaxial layer has a first trench therein, the body layer has a second trench therein, the first trench is disposed below the second trench, and first trench is narrower than the second trench. A first insulating layer is disposed on a surface of the first trench. A first conductive layer fills up the first trench and extends into the second trench. A second conductive layer fills up the second trench. A second insulating layer is disposed between the second conductive layer and each of the body layer and the first conductive layer. A dielectric layer is disposed on the epitaxial layer and covers the second conductive layer. Two doped regions are disposed in the body layer respectively beside the second trench.

Abstract: A trench gate MOSFET is provided. An epitaxial layer is disposed on a substrate. A body layer is disposed in the epitaxial layer. The epitaxial layer has a first trench therein, the body layer has a second trench therein, and the first trench is disposed below the second trench. A first insulating layer is disposed on a surface of the first trench. A second insulating layer is disposed in the first trench. A first conductive layer is disposed between the first and second insulating layers. A second conductive layer is disposed in the second trench. A third insulating layer is disposed between the second conductive layer and the body layer and between the second conductive layer and the first conductive layer. A dielectric layer is disposed on the epitaxial layer and covers the second conductive layer. Two doped regions are disposed in the body layer respectively beside the second trench.

Abstract: A method of forming a trench gate MOSFET is provided. An epitaxial layer is formed on a substrate. A trench is formed in the epitaxial layer. A first insulating layer is conformally formed on surfaces of the epitaxial layer and the trench. A first conductive layer is formed at the bottom of the trench. A portion of the first insulating layer is removed to form a second insulating layer exposing an upper portion of the first conductive layer. An oxidation process is performed to oxidize the first conductive layer to a third insulating layer, wherein a fourth insulating layer is simultaneously formed on the surface of the epitaxial layer and on the sidewall of the trench. A second conductive layer is formed in the trench. Two body layers are formed in the epitaxial layer beside the trench. Two doped regions are formed in the body layers respectively beside the trench.

Abstract: A trench gate MOSFET is provided. An epitaxial layer is disposed on a substrate. A body layer is disposed in the epitaxial layer. The epitaxial layer has a first trench therein, the body layer has a second trench therein, and the first trench is disposed below the second trench. A first conductive layer is disposed in the first trench. A first insulating layer is disposed between the first conductive layer and the epitaxial layer. A second conductive layer is disposed on a sidewall of the second trench. A second insulating layer is disposed between the second conductive layer and the body layer, and between the second conductive layer and the first conductive layer. A dielectric layer is disposed on the epitaxial layer and fills up the second trench. Two doped regions are disposed in the body layer respectively beside the second trench.

Abstract: A method of forming a trench gate MOSFET is provided. An epitaxial layer is formed on a substrate. A trench is formed in the epitaxial layer. A first insulating layer is conformally formed on surfaces of the epitaxial layer and the trench. A first conductive layer is formed at the bottom of the trench. A portion of the first insulating layer is removed to form a second insulating layer exposing an upper portion of the first conductive layer. An oxidation process is performed to oxidize the first conductive layer to a third insulating layer, wherein a fourth insulating layer is simultaneously formed on the surface of the epitaxial layer and on the sidewall of the trench. A second conductive layer is formed in the trench. Two body layers are formed in the epitaxial layer beside the trench. Two doped regions are formed in the body layers respectively beside the trench.

Abstract: A high-voltage semiconductor device structure is provided, which includes a drain structure having two curved structures that are insulatedly adjacent to each other and alternatively arranged, and a source structure, a drain extension structure, and a gate structure formed between the two curved structures. By using the curved structures with alternatively arranged configuration, an electrode terminal with a small curvature radius is prevented from being produced, and the electric field accumulation effect is partially eliminated, thereby increasing the breakdown voltage. Meanwhile, the curved structure with alternatively arranged configuration not only reduces the ON resistance, but also utilizes the space effectively, thus, the integration of the semiconductor device on the chip is enhanced, so that the miniaturization requirement of an electronic device is satisfied.

Abstract: A high-voltage semiconductor device structure is provided, which includes a drain structure having two curved structures that are insulatedly adjacent to each other and alternatively arranged, and a source structure, a drain extension structure, and a gate structure formed between the two curved structures. By using the curved structures with alternatively arranged configuration, an electrode terminal with a small curvature radius is prevented from being produced, and the electric field accumulation effect is partially eliminated, thereby increasing the breakdown voltage. Meanwhile, the curved structure with alternatively arranged configuration not only reduces the ON resistance, but also utilizes the space effectively, thus, the integration of the semiconductor device on the chip is enhanced, so that the miniaturization requirement of an electronic device is satisfied.

Abstract: A high voltage laterally double-diffused metal oxide semiconductor (LDMOS) stricture is characterized as follows: the second source electrode metal layer connected to the first source electrode metal layer protrudes out of a certain length relative to the first source electrode metal layer of the source electrode region connected thereto. The second drain electrode metal layer connected to the first drain electrode metal layer protrudes out of a certain length relative to the first drain electrode metal layer of the drain electrode region. The protruded length overlaps more portions of the drift layer than the first source electrode metal layer and the first drain electrode metal layer disposed below, to reduce the electric field concentration of the gate electrode interface or the interface between the N+ type drain electrode layer and the N-type extended drift layer.

Abstract: A high voltage laterally double-diffused metal oxide semiconductor (LDMOS) structure is characterized as follows: the second source electrode metal layer connected to the first source electrode metal layer protrudes out of a certain length relative to the first source electrode metal layer of the source electrode region connected thereto. The second drain electrode metal layer connected to the first drain electrode metal layer protrudes out of a certain length relative to the first drain electrode metal layer of the drain electrode region. The protruded length overlaps more portions of the drift layer than the first source electrode metal layer and the first drain electrode metal layer disposed below, to reduce the electric field concentration of the gate electrode interface or the interface between the N+ type drain electrode layer and the N-type extended drift layer.

Abstract: A process for reducing the dark current generation of an image sensor cell, fabricated on a semiconductor substrate, has been developed. The process features the use of polysilicon pad structure, formed simultaneously with a polysilicon gate structure of a reset transistor, with the polysilicon pad structure located overlying, and contacting, a portion of the top surface of the photodiode element, of the image sensor cell. A small diameter opening, in a composite polysilicon-silicon oxide layer, exposes the portion of photodiode element to be contacted by the polysilicon pad structure. The small diameter opening is created using a procedure which allows the surface of the photodiode element, exposed in the small diameter opening to experience only a minimum of RIE processing at end point, thus minimizing damage to the surface of the photodiode element, and thus reducing dark current generation.

Abstract: An active pixel sensor cell, and the process for forming the active pixel sensor cell, featuring a pinned photodiode structure, and a readout region, located in a region of the pinned photodiode structure, has been developed. The process features the formation of a N+ readout region, performed simultaneously with the formation of the N+ source/drain region of the reset transistor, however with the N+ readout region placed in an area to be used for the pinned photodiode structure. The pinned photodiode structure is next formed via formation of a lightly doped N type well region, used as the lower segment of the pinned photodiode structure, followed by the formation of P+ region, used as the top segment of the pinned photodiode structure, with the N+ readout region, surrounded by the P+ region.

Abstract: A method of forming an image sensor is disclosed. A partially processed semiconductor wafer is provide, containing p-type and/or n-type regions which are bounded by isolation regions and with gate oxide layers grown on the surfaces upon which gate electrode structures are disposed, some of said gate electrode structures will serve as gate electrodes of image sensor transistors. Ions are implanted to form source/drain structures about the said gate electrode structures. To form photodiodes ions are implanted in two steps overlapping a source/drain region. A deeper implant provides a low charge carrier density region and a shallow implant provides a high charge carrier density region near the surface. A blanket transparent insulating layer is deposited.

Abstract: An active pixel sensor cell, and the process for forming the active pixel sensor cell, featuring a pinned photodiode structure, and a readout region, located in a region of the pinned photodiode structure, has been developed. The process features the formation of a N+ readout region, performed simultaneously with the formation of the N+ source/drain region of the reset transistor, however with the N+ readout region placed in an area to be used for the pinned photodiode structure. The pinned photodiode structure is next formed via formation of a lightly doped N type well region, used as the lower segment of the pinned photodiode structure, followed by the formation of P+ region, used as the top segment of the pinned photodiode structure, with the N+ readout region, surrounded by the P+ region.

Abstract: An active pixel sensor cell, and the process for forming the active pixel sensor cell, featuring a pinned photodiode structure, and a readout region, located in a region of the pinned photodiode structure, has been developed. The process features the formation of a N+ readout region, performed simultaneously with the formation of the N+ source/drain region of the reset transistor, however with the N+ readout region placed in an area to be used for the pinned photodiode structure. The pinned photodiode structure is next formed via formation of a lightly doped N type well region, used as the lower segment of the pinned photodiode structure, followed by the formation of P+ region, used as the top segment of the pinned photodiode structure, with the N+ readout region, surrounded by the P+ region.

Abstract: A method of forming an image sensor is disclosed. A partially processed semiconductor wafer is provide, containing p-type and/or n-type regions which are bounded by isolation regions and with gate oxide layers grown on the surfaces upon which gate electrode structures are disposed, some of said gate electrode structures will serve as gate electrodes of image sensor transistors. Ions are implanted to form source/drain structures about the said gate electrode structures, with an extended region for source drains bordering photodiode regions. Ions are implanted to form photodiodes, overlapping the extended bordering source drain regions. A blanket transparent insulating layer is deposited.

Abstract: A process of fabricating an image sensor cell, on a semiconductor substrate, with the image sensor cell exhibiting low dark current generation, and high signal to noise ratio, has been developed. The process features the use of a photoresist shape, used to protect a previously formed photodiode element, from an reactive ion etching procedure, used to define insulator spacers on the sides of a polysilicon gate structure, of a reset transistor structure This process sequence avoids damage to the surface of an N type component, of the photodiode element, resulting in the improved electrical characteristics, when compared to counterpart image sensor cells, in which the photodiode element was subjected to the insulator spacer definition procedure.