Abstract: A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.

Abstract: A flash memory cell structure is provided. A semiconductor structure includes a semiconductor substrate, a floating gate overlying the semiconductor substrate, a word-line adjacent to the floating gate, an erase gate adjacent to a side of the floating gate opposite the word-line, a first sidewall disposed between the floating gate and the word-line, and a second sidewall disposed between the floating gate and the erase gate. The first sidewall has a first characteristic and the second sidewall has a second characteristic. The first characteristic is different from the second characteristic.

Abstract: A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.

Abstract: A capacitor and methods for forming the same are provided. The method includes forming a bottom electrode; treating the bottom electrode in an oxygen-containing environment to convert a top layer of the bottom electrode into a buffer layer; forming an insulating layer on the buffer layer; and forming a top electrode over the insulating layer.

Abstract: A method for forming a semiconductor structure includes providing a substrate; forming a gate stack of a flash memory cell, wherein a top portion of the gate stack comprises a capping layer; forming a gate having at least a portion over the capping layer; and reducing a thickness of the portion of the gate over the capping layer. The topography height difference between the flash memory cell and MOS devices on the same chip is reduced.

Abstract: A flash memory cell structure is provided. A semiconductor structure includes a semiconductor substrate, a floating gate overlying the semiconductor substrate, a word-line adjacent to the floating gate, an erase gate adjacent to a side of the floating gate opposite the word-line, a first sidewall disposed between the floating gate and the word-line, and a second sidewall disposed between the floating gate and the erase gate. The first sidewall has a first characteristic and the second sidewall has a second characteristic. The first characteristic is different from the second characteristic.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first floating gate on the semiconductor substrate, the floating gate having a concave side surface; a first control gate on the first floating gate; a first spacer adjacent to the first control gate; a first word line adjacent a first side of the first floating gate with a first distance; and an erase gate adjacent a second side of the first floating gate with a second distance less than the first distance, the second side being opposite the first side.

Abstract: A method for fabricating a gated semiconductor device, and the device resulting from performing the method. In a preferred embodiment, the method includes forming a hard mask for use in gate formation on one or more layers of alternately insulating and conducting material that have been formed on a substrate. The hard mask preferably includes three layers; a lower nitride layer, a middle oxide, and an upper nitride layer. In this embodiment, the middle oxide layer is formed with the rest of the hard mask, and then reduced in a lateral dimension, preferably using a DHF dip. A dielectric layer formed over the gate structure, including the hard mask, then etched back, self-aligns to be reduced-dimension oxide layer. In addition, where two conducting, that is gate layers are present, the lower layer is laterally reduced in dimension on at least one side to create an undercut.

Abstract: An integrated circuit structure includes a dielectric layer having an upper portion and a lower portion. The dielectric layer is either an inter-layer dielectric (ILD) or an inter-metal dielectric (IMD). A phase change random access memory (PCRAM) cell includes a phase change strip, wherein the phase change strip is on the lower portion and has a top surface lower than a top surface of the dielectric layer, and a bottom surface higher than a bottom surface of the dielectric layer. A first conductive column is electrically connected to the phase change strip. The first conductive column extends from the top surface of the dielectric layer down into the dielectric layer. A second conductive column is in a peripheral region. The second conductive column extends from the top surface of the dielectric layer down into the dielectric layer. The first conductive column and the second conductive column have different heights.

Abstract: A semiconductor device with an embedded capacitor structure. A dielectric layer is disposed on a substrate, having a contact opening exposing the substrate and a trench opening above the contact opening. A first metal electrode layer is conformally disposed over the sidewalls and bottoms of the contact and trench openings. A second metal electrode layer is conformally disposed over the sidewalls and bottoms of the contact and trench openings. A capacitor dielectric layer is interposed between the first and second metal electrode layers. A method for fabricating the semiconductor device is also disclosed.

Abstract: A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion. The semiconductor structure further includes a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a first floating gate on the semiconductor substrate, the floating gate having a concave side surface; a first control gate on the first floating gate; a first spacer adjacent to the first control gate; a first word line adjacent a first side of the first floating gate with a first distance; and an erase gate adjacent a second side of the first floating gate with a second distance less than the first distance, the second side being opposite the first side.

Abstract: A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion. The semiconductor structure further includes a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate.

Abstract: A semiconductor structure includes a semiconductor substrate; a tunneling layer on the semiconductor substrate; a source region adjacent the tunneling layer; and a floating gate on the tunneling layer. The floating gate comprises a first edge having an upper portion and a lower portion, wherein the lower portion is recessed from the upper portion. The semiconductor structure further includes a blocking layer on the floating gate, wherein the blocking layer has a first edge facing a same direction as the first edge of the floating gate.

Abstract: A method of manufacturing a semiconductor device, wherein a gate structure is formed over a substrate, an interconnect layer is formed over the gate structure and the substrate, and a cap layer is formed over the interconnect layer. The interconnect layer and the cap layer are then planarized to form a substantially planar surface. A mask layer, such as an oxide mask layer, is formed over the planarized portions of the interconnect layer, and the planarized cap layer and portions of the interconnect layer are removed by etching around the mask layer.

Abstract: A method for forming a semiconductor device with a bonding pad is disclosed. A first substrate having a device area and a bonding area is provided, wherein the first substrate has an upper surface and a bottom surface. Semiconductor elements are formed on the upper surface of the first substrate in the device area. A first inter-metal dielectric layer is formed on the upper surface of the substrate in the bonding area. A lowermost metal pattern is formed in the first inter-metal dielectric layer, wherein the lowermost metal pattern serves as the bonding pad. An opening through the first substrate is formed to expose the lowermost metal pattern.

Abstract: A flash memory cell structure is provided. A semiconductor structure includes a semiconductor substrate, a floating gate overlying the semiconductor substrate, a word-line adjacent to the floating gate, an erase gate adjacent to a side of the floating gate opposite the word-line, a first sidewall disposed between the floating gate and the word-line, and a second sidewall disposed between the floating gate and the erase gate. The first sidewall has a first characteristic and the second sidewall has a second characteristic. The first characteristic is different from the second characteristic.

Abstract: An integrated circuit structure includes a dielectric layer having an upper portion and a lower portion. The dielectric layer is either an inter-layer dielectric (ILD) or an inter-metal dielectric (IMD). A phase change random access memory (PCRAM) cell includes a phase change strip, wherein the phase change strip is on the lower portion and has a top surface lower than a top surface of the dielectric layer, and a bottom surface higher than a bottom surface of the dielectric layer. A first conductive column is electrically connected to the phase change strip. The first conductive column extends from the top surface of the dielectric layer down into the dielectric layer. A second conductive column is in a peripheral region. The second conductive column extends from the top surface of the dielectric layer down into the dielectric layer. The first conductive column and the second conductive column have different heights.

Abstract: A method includes forming an amorphous carbon layer over a first dielectric layer formed over a substrate, forming a second dielectric layer over the amorphous carbon layer; and forming an opening within the amorphous carbon layer and second dielectric layer by a first etch process to partially expose a top surface of the first dielectric layer. A substantially conformal metal-containing layer is formed over the second dielectric layer and within the opening. The second dielectric layer and a portion of the metal-containing layer are removed. The amorphous carbon layer is removed by an oxygen-containing plasma process to expose a top surface of the first dielectric layer. An insulating layer is formed over the metal-containing layer, and a second metal-containing layer is formed over the insulating layer to form a capacitor.

Abstract: An improved method for fabricating floating gate structures of flash memory cells having reduced and more uniform forward tunneling voltages. The method may include the steps of: forming at least two floating gates over a substrate; forming a mask over each of the floating gates, each of the masks having a portion, adjacent to a tip of a respective one of the floating gates, of a given thickness, wherein the given thicknesses of the mask portions are different from one another; and etching the masks to reduce the different given thicknesses of the mask portions to a reduced thickness wherein the reduced thickness portions of the mask are of a uniform thickness.