Abstract: A new method to form MOS gates in an integrated circuit device is achieved. The method is particularly useful for forming floating gates in split gate flash transistors. The method comprises providing a substrate. A dielectric layer is formed overlying the substrate. A conductor layer is formed overlying the dielectric layer. A first masking layer is deposited overlying the conductor layer. The first masking layer is patterned to selectively expose the conductor layer. A second masking layer is deposited overlying the first masking layer and the conductor layer. The second masking layer is etched back to form spacers on sidewalls of the first masking layer. The conductor layer is etched through where exposed by the first masking layer and the spacers to thereby form MOS gates in the manufacture of the integrated circuit device.

Abstract: A new method to form MOS gates in an integrated circuit device is achieved. The method is particularly useful for forming floating gates in split gate flash transistors. The method comprises providing a substrate. A dielectric layer is formed overlying the substrate. A conductor layer is formed overlying the dielectric layer. A first masking layer is deposited overlying the conductor layer. The first masking layer is patterned to selectively expose the conductor layer. A second masking layer is deposited overlying the first masking layer and the conductor layer. The second masking layer is etched back to form spacers on sidewalls of the first masking layer. The conductor layer is etched through where exposed by the first masking layer and the spacers to thereby form MOS gates in the manufacture of the integrated circuit device.

Abstract: A split gate FET wordline electrode structure and method for forming the same including an improved polysilicon etching process including providing a semiconductor wafer process surface comprising first exposed polysilicon portions and adjacent oxide portions; forming a first oxide layer on the exposed polysilicon portions; blanket depositing a polysilicon layer on the first exposed polysilicon portions and adjacent oxide portions; forming a hardmask layer on the polysilicon layer; carrying out a multi-step reactive ion etching (RIE) process to etch through the hardmask layer and etch through a thickness portion of the polysilicon layer to form second polysilicon portions adjacent the oxide portions having upward protruding outer polysilicon fence portions; contacting the semiconductor wafer process surface with an aqueous HF solution; and, carrying out a downstream plasma etching process to remove polysilicon fence portions.

Abstract: A method of fabricating word-line spacers comprising the following steps. A substrate having an inchoate split-gate flash memory structure formed thereover is provided. A conductive layer is formed over the substrate and the inchoate split-gate flash memory structure. The conductive layer having: a upper portion and lower vertical portions over the inchoate split-gate flash memory structure; and lower horizontal portions over the substrate. A dual-thickness oxide layer is formed over the conductive layer and has a greater thickness over the upper portion of the conductive layer. The oxide layer is partially etched back to remove at least the oxide layer from over the lower horizontal portions of the conductive layer to expose the underlying portions of the conductive layer.

Abstract: A new method to form MOS gates in an integrated circuit device is achieved. The method is particularly useful for forming floating gates in split gate flash transistors. The method comprises providing a substrate. A dielectric layer is formed overlying the substrate. A conductor layer is formed overlying the dielectric layer. A first masking layer is deposited overlying the conductor layer. The first masking layer is patterned to selectively expose the conductor layer. A second masking layer is deposited overlying the first masking layer and the conductor layer. The second masking layer is etched back to form spacers on sidewalls of the first masking layer. The conductor layer is etched through where exposed by the first masking layer and the spacers to thereby form MOS gates in the manufacture of the integrated circuit device.

Abstract: A method for integrating copper with an MIM capacitor during the formation the MIM capacitor. The MIM capacitor is generally formed upon a substrate and at least one copper layer is deposited upon the substrate and layers thereof to form at least one metal layer from which the MIM capacitor is formed, such that the MIM capacitor may be adapted for use with an embedded DRAM device. The MIM capacitor comprises a low-temperature MIM capacitor. At least one DRAM crown photo layer may be formed upon the substrate and layers thereof to form the MIM capacitor. The number of additional lithographic steps required in BEOL manufacturing operations is thus only one, while the capacitance of the MIM capacitor can be improved greatly because the sequential process of the DRAM crown photo patterning steps may be altered.

Abstract: A method of defining composite insulator spacers on the sides of conductive gate structures, with reduced risk of semiconductor damage at end point of the composite insulator spacer definition procedure, has been developed. The method features initial deposition of a thin underlying, silicon rich, undoped silica glass (USG), layer, comprised with a refractive index greater than 1.55. After deposition of a TEOS silicon oxide layer a first phase of an anisotropic RIE procedure, using a CF4/CHF3 etch chemistry, is used to selectively define a silicon oxide spacer component, with the first phase of the etch procedure terminating on the underlying silicon rich, USG layer.

Abstract: A method for forming a spacer layer adjoining a substantially vertical first sidewall of a topographic feature within a microelectronic product employs an anisotropic etching of a reentrant spacer material layer formed upon the topographic feature. The spacer layer is formed at least in part with a substantially vertical second sidewall laterally separated from the substantially vertical first sidewall. The method is useful for forming spacer layers within field effect transistor devices.

Abstract: A method for removing polymer containing residues from a semiconductor wafer including metal containing features including providing a semiconductor wafer having a process surface including metal containing features said process surface at least partially covered with polymer containing residues; and, subjecting the semiconductor wafer to a series of cleaning steps including sequentially exposing the process surface to at least one primary solvent and at least one intermediate solvent the at least one intermediate solvent comprising an ammonium nitrate containing solution.

Abstract: A method for forming a spacer layer adjoining a substantially vertical first sidewall of a topographic feature within a microelectronic product employs an anisotropic etching of a reentrant spacer material layer formed upon the topographic feature. The spacer layer is formed at least in part with a substantially vertical second sidewall laterally separated from the substantially vertical first sidewall. The method is useful for forming spacer layers within field effect transistor devices.

Abstract: A method of defining composite insulator spacers on the sides of conductive gate structures, with reduced risk of semiconductor damage at end point of the composite insulator spacer definition procedure, has been developed. The method features initial deposition of a thin underlying, silicon rich, undoped silica glass (USG), layer, comprised with a refractive index greater than 1.55. After deposition of a TEOS silicon oxide layer a first phase of an anisotropic RIE procedure, using a CF4/CHF3 etch chemistry, is used to selectively define a silicon oxide spacer component, with the first phase of the etch procedure terminating on the underlying silicon rich, USG layer.

Abstract: A method for integrating copper with an MIM capacitor during the formation the MIM capacitor. The MIM capacitor is generally formed upon a substrate and at least one copper layer is deposited upon the substrate and layers thereof to form at least one metal layer from which the MIM capacitor is formed, such that the MIM capacitor may be adapted for use with an embedded DRAM device. The MIM capacitor comprises a low-temperature MIM capacitor. At least one DRAM crown photo layer may be formed upon the substrate and layers thereof to form the MIM capacitor. The number of additional lithographic steps required in BEOL manufacturing operations is thus only one, while the capacitance of the MIM capacitor can be improved greatly because the sequential process of the DRAM crown photo patterning steps may be altered.

Abstract: A process for defining an aluminum based structure, on an underlying titanium nitride shape, via use of a two step dry etching procedure, has been developed. A first iteration of the two step dry etching process features initial definition of the aluminum based structure, on an underlying titanium nitride layer, using a photoresist shape as an etch mask, performed in a chlorine based environment, with the first dry etching step terminating at the appearance of the titanium nitride layer. A second dry etching step features the introduction of a fluorine based etchant, to the chlorine based environment, forming a protective aluminum fluoride layer on the exposed sides of the aluminum based structure during definition of the titanium nitride shape. A second iteration of the two step dry etching process features the removal of the masking photoresist shape after definition of the aluminum based structure, via the first dry etching step.

Abstract: A new method is provided for the creation of spacers for the CMOS gate electrode. A layer of a spacer material is deposited over the gate structure; a layer of photoresist is deposited over the layer of spacer material. The layer of photoresist of the invention is partially stripped removing the photoresist from above the gate structure and providing a thinner layer of photoresist over the surrounding layer of spacer material. The layer of spacer material is partially etched whereby the layer of photoresist serves as a partial etch stop layer. The remainder of the photoresist is removed, the spacer material is further etched using a dry etch whereby a thin layer of spacer material (oxide) remains deposited over the surface of the substrate. As a final step the thin layer of spacer material (oxide) is removed from the surface of the substrate using a wet etch.

Abstract: A method is disclosed for forming an aluminum bump on an integrated circuit (IC) chip without leaving any metal residue on the passivation layer of the chip. This is accomplished by planarizing the passivation layer with spin-on-glass (SOG) and then forming a PECVD oxide as a sacrificial layer over the SOG, and etching through these layers to form an opening over a metal pad underlying the passivation layer. Then, a layer of aluminum is deposited over the substrate, including the opening, to form an aluminum bump. Aluminum bump is next formed by etching through a patterned oxide which acts as a hard mask over the aluminum layer. The SOG is then removed leaving the passivation layer free of any aluminum residue.

Abstract: A method for forming a CMOS image sensor spacer structure. A polysilicon gate electrode is formed on a substrate; a thin layer of first dielectric is deposited over the exposed surfaces of the gate electrode and the top of the substrate. Next a second layer of dielectric is deposited after which etching is performed to create the electrode spacer. The deposited second layer of dielectric serves as an etch stop and prevents damage to the substrate surface between spacers of the gate electrodes. An alternate method uses a thin ply layer as the stop layer and, in so doing, source/drain damage caused by the white pixel problem.

Abstract: A method for cleaning a plasma etch chamber is described which can be carried out by first terminating an etch process by stopping a process gas flow into the chamber, then maintaining a RF power in the etch chamber, and flowing a cleaning gas consists of at least one inert gas and oxygen through the chamber at a flow rate higher than the flow rate for the process gas for a length of time sufficient to evacuate substantially all the contaminating byproducts formed by the process gas. A suitable cleaning gas contains at least one inert gas of Ar, He, or N.sub.2 mixed with O.sub.2. A sufficient length of time for the cleaning process is at least 5 seconds, and preferably at least 10 seconds.

Abstract: An improved and new method of forming tungsten plugs on contact holes in semiconductor integrated circuit devices has been developed. The method uses a two step tungsten etchback process wherein redeposition of etch byproducts is surpressed, residue removal is enhanced, and the overetching requirement is reduced. The result is a more reliable, lower cost, higher yield process.

Abstract: The present invention provides a method of forming a Self-aligned contact with fewer process steps. The invention includes a three step insitu process of (1) a first descum step, (2) a dry etch step and (3) second descum step followed by (4) an isotropic etch step. The process comprises coating, exposing, and developing, and baking a photoresist layer over an insulating layer. In an important process stage, three steps are performed: (1) an insitu first descum step, (2) a dry etch step and (3) a second descum step. The dry etch step forms a first self-aligned contact opening. Next, the first contact opening is isotropically etched forming a smoother second contact opening 44. The photoresist layer 30 is then removed. Lastly, a metal layer 60 is deposited in said second self aligned contact opening 44. The invention reduces cycle time and eliminates several process steps while maintaining high yields. The smoother second contact opening 44 provides better metal adhesion.

Abstract: Apparatus and method are described for etching in liquid acids at high temperatures, notably silicon nitride in phosphoric acid. This has been achieved by providing an apparatus in which the liquid acid evaporant is condensed and returned to the main volume of acid by way of a pH meter whose output is used to control the flow of additional pure water into the main system. Alternatively, a conductivity meter, located in the etch bath, may be used for the same purpose. Undiluted acid is automatically added to the main system, as needed, under the control of a level sensor that senses the quantity of liquid in the main volume. Thus the pH or conductivity of the etchant is constantly being monitored and maintained at the desired level. Since the aqueous concentration remains steady throughout, sudden unexpected, and potentially dangerous, increases in the rate of boiling do not occur.