Patents by Inventor Chih Wang

Chih Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240133745
    Abstract: A temperature sensing device includes a substrate, a first reflective module, a first window cover, and a dual thermopile sensor. The first reflective module is disposed on the substrate, including a first mirror chamber with a narrow field of view (FOV), and the first reflective module focuses a thermal radiation from measured object to a first image plane in the first mirror chamber. The first window cover is disposed on the first reflective module, and the first window cover allows a selected band of the thermal radiation to pass through. The dual thermopile sensor is disposed on the substrate and located in the first mirror chamber, and the dual thermopile sensor senses a temperature data from the first image plane. Additional second reflective module, LED source plus pin hole with same FOV of dual thermopile sensor can illuminate the measured object for ease of placement of object to be heated.
    Type: Application
    Filed: October 19, 2022
    Publication date: April 25, 2024
    Inventors: Chein-Hsun WANG, Ming LE, Tung-Yang LEE, Yu-Chih LIANG, Wen-Chie HUANG, Chen-Tang HUANG, Jenping KU
  • Publication number: 20240135990
    Abstract: A resistive memory apparatus including a memory cell array, at least one dummy transistor and a control circuit is provided. The memory cell array includes a plurality of memory cells. Each of the memory cells includes a resistive switching element. The dummy transistor is electrically isolated from the resistive switching element. The control circuit is coupled to the memory cell array and the dummy transistor. The control circuit is configured to provide a first bit line voltage, a source line voltage and a word line voltage to the dummy transistor to drive the dummy transistor to output a saturation current. The control circuit is further configured to determine a value of a second bit line voltage for driving the memory cells according to the saturation current. In addition, an operating method and a memory cell array of the resistive memory apparatus are also provided.
    Type: Application
    Filed: December 28, 2023
    Publication date: April 25, 2024
    Applicant: Winbond Electronics Corp.
    Inventors: Ming-Che Lin, Min-Chih Wei, Ping-Kun Wang, Yu-Ting Chen, Chih-Cheng Fu, Chang-Tsung Pai
  • Patent number: 11967622
    Abstract: Embodiments provide a dielectric inter block disposed in a metallic region of a conductive line or source/drain contact. A first and second conductive structure over the metallic region may extend into the metallic region on either side of the inter block. The inter block can prevent etchant or cleaning solution from contacting an interface between the first conductive structure and the metallic region.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: April 23, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Te-Chih Hsiung, Jyun-De Wu, Yi-Chen Wang, Yi-Chun Chang, Yuan-Tien Tu
  • Patent number: 11968646
    Abstract: Wireless communications systems and methods related to communicating control information are provided. A method of wireless communication performed by a user equipment (UE) may include sensing an interference level of at least one frequency, selecting, based on the interference level, a frequency, and communicating sidelink control information (SCI) in the selected frequency.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: April 23, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Yisheng Xue, Xiaojie Wang, Jing Sun, Chih-Hao Liu, Xiaoxia Zhang
  • Patent number: 11964409
    Abstract: A multi-shot moulding part structure includes a first structural part, an ink decoration layer, and a second structural part. The first structural part has a first area surface, a second area surface, and a joining surface located on the second area surface. The joining surface is non-parallel to the second area surface. The ink decoration layer is spread on the first area surface and the second area surface, but not on the joining surface. The second structural part is combined with the first structural part and covers the second area surface. The second structural part touches the joining surface. By the second structural part touching the joining surface of the first structural part that is not coated with the ink decoration layer, the structural bonding strength between the first structural part and the second structural part is enhanced.
    Type: Grant
    Filed: August 31, 2021
    Date of Patent: April 23, 2024
    Assignees: Inventec (Pudong) Technology Corp., Inventec Corporation
    Inventors: Wen-Ching Lin, Ting-Yu Wang, Fa-Chih Ke, Yu-Ling Lin, Wen-Hsiang Chen
  • Patent number: 11964881
    Abstract: A method for making iridium oxide nanoparticles includes dissolving an iridium salt to obtain a salt-containing solution, mixing a complexing agent with the salt-containing solution to obtain a blend solution, and adding an oxidating agent to the blend solution to obtain a product mixture. A molar ratio of a complexing compound of the complexing agent to the iridium salt is controlled in a predetermined range so as to permit the product mixture to include iridium oxide nanoparticles.
    Type: Grant
    Filed: July 27, 2020
    Date of Patent: April 23, 2024
    Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITY
    Inventors: Pu-Wei Wu, Yi-Chieh Hsieh, Han-Yi Wang, Kuang-Chih Tso, Tzu-Ying Chan, Chung-Kai Chang, Chi-Shih Chen, Yu-Ting Cheng
  • Publication number: 20240128093
    Abstract: A manufacturing method of an electronic device includes that a chip package is mounted on a circuit board. And an exposed surface of the chip package is bombarded with plasma to clean the surface. The manufacturing method of the electronic device of the application can effectively clean the chip package without reducing the reliability of the electronic device.
    Type: Application
    Filed: December 2, 2022
    Publication date: April 18, 2024
    Applicant: ASUSTeK COMPUTER INC.
    Inventors: Xu Wang, Chih-Kuan Liu
  • Publication number: 20240129012
    Abstract: A wearable device includes a frame element and a dielectric substrate. The frame element includes a first metal element, a second metal element, and a third metal element. A first gap is provided between the first metal element and the second metal element. A second gap is provided between the second metal element and the third metal element. A third gap is provided between the third metal element and the first metal element. The dielectric substrate is surrounded by the first metal element, the second metal element, and the third metal element. A first antenna element is formed by the first metal element. A second antenna element is formed by the second metal element. A third antenna element is formed by the third metal element.
    Type: Application
    Filed: December 6, 2022
    Publication date: April 18, 2024
    Inventors: Jing-Yao XU, Chung-Ting HUNG, Chun-Yuan WANG, Chu-Yu TANG, Yi-Chih LO, Yu-Chen ZHAO, Chih-Tsung TSENG
  • Patent number: 11961777
    Abstract: A package structure and a method of forming the same are provided. The package structure includes a first die, a second die, a first encapsulant, and a buffer layer. The first die and the second die are disposed side by side. The first encapsulant encapsulates the first die and the second die. The second die includes a die stack encapsulated by a second encapsulant encapsulating a die stack. The buffer layer is disposed between the first encapsulant and the second encapsulant and covers at least a sidewall of the second die and disposed between the first encapsulant and the second encapsulant. The buffer layer has a Young's modulus less than a Young's modulus of the first encapsulant and a Young's modulus of the second encapsulant.
    Type: Grant
    Filed: June 27, 2022
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-Chih Chen, Chien-Hsun Lee, Chung-Shi Liu, Hao-Cheng Hou, Hung-Jui Kuo, Jung-Wei Cheng, Tsung-Ding Wang, Yu-Hsiang Hu, Sih-Hao Liao
  • Patent number: 11961893
    Abstract: Improved conductive contacts, methods for forming the same, and semiconductor devices including the same are disclosed. In an embodiment, a semiconductor device includes a first interlayer dielectric (ILD) layer over a transistor structure; a first contact extending through the first ILD layer, the first contact being electrically coupled with a first source/drain region of the transistor structure, a top surface of the first contact being convex, and the top surface of the first contact being disposed below a top surface of the first ILD layer; a second ILD layer over the first ILD layer and the first contact; and a second contact extending through the second ILD layer, the second contact being electrically coupled with the first contact.
    Type: Grant
    Filed: June 18, 2021
    Date of Patent: April 16, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Te-Chih Hsiung, Jyun-De Wu, Yi-Chen Wang, Yi-Chun Chang, Yuan-Tien Tu
  • Patent number: 11962239
    Abstract: A control circuit of a power converter and a control method thereof are provided. The control circuit includes an error amplifier, a controller, a digital filter, and a digital pulse width signal modulator. The error amplifying circuit is coupled to an output terminal of the power converter and provides a digital error signal. The controller provides a first working parameter corresponding to the first external control command when receiving a first external control command. The digital filter generates a current digital compensation value. The digital pulse width signal modulator generates a pulse width modulation signal. The controller provides a second working parameter corresponding to the second external control command when receiving a second external control command. The controller calculates a transition value according to the second working parameter and the current digital compensation value. The controller provides the second working parameter and the transition value to the digital filter.
    Type: Grant
    Filed: September 16, 2022
    Date of Patent: April 16, 2024
    Assignee: uPI Semiconductor Corp.
    Inventors: Yun-Kuo Lee, Wei-Hsiang Wang, Yen-Chih Lin, Wei-Hsiu Hung
  • Publication number: 20240115650
    Abstract: The present invention features interferon-free therapies for the treatment of HCV. Preferably, the treatment is over a shorter duration of treatment, such as no more than 12 weeks. In one aspect, the treatment comprises administering at least two direct acting antiviral agents to a subject with HCV infection, wherein the treatment lasts for 12 weeks and does not include administration of either interferon or ribavirin, and said at least two direct acting antiviral agents comprise (a) Compound 1 or a pharmaceutically acceptable salt thereof and (b) Compound 2 or a pharmaceutically acceptable salt thereof.
    Type: Application
    Filed: December 11, 2023
    Publication date: April 11, 2024
    Applicant: ABBVIE INC.
    Inventors: Walid M. Awni, Barry M. Bernstein, Andrew L. Campbell, Sandeep Dutta, Chih-Wei Lin, Wei Liu, Rajeev M. Menon, Thomas J. Podsadecki, Tianli Wang, Sven Mensing
  • Publication number: 20240119200
    Abstract: A method of building a characteristic model includes: acquiring raw electrical data from a measurement system outside one or more processing units; acquiring operational state-related data from an information collector inside the one or more processing units; performing a data annealing process on the raw electrical data and the operational state-related data to obtain and purified electrical data and purified operational state-related data; and performing a machine learning (ML)-based process to build the characteristic model based on the purified electrical data and the purified operational state-related data.
    Type: Application
    Filed: October 3, 2023
    Publication date: April 11, 2024
    Applicant: MEDIATEK INC.
    Inventors: Yu-Jen Chen, Chien-Chih Wang, Wen-Wen Hsieh, Ying-Yi Teng
  • Patent number: 11957047
    Abstract: A composition of materials including a first compound having a structure according to Formula I
    Type: Grant
    Filed: August 15, 2022
    Date of Patent: April 9, 2024
    Assignee: UNIVERSAL DISPLAY CORPORATION
    Inventors: Lichang Zeng, Suman Layek, Pierre-Luc T. Boudreault, Zeinab Elshenawy, Gregg Kottas, Alexey Borisovich Dyatkin, Scott Joseph, Vadim Adamovich, Chuanjun Xia, Ting-Chih Wang, Walter Yeager
  • Patent number: 11952445
    Abstract: A Ziegler-Natta catalyzed ethylene/alpha-olefins copolymer is provided having sporadic long chain branches and reversed comonomer composition distribution or short chain branching distribution (SCBD) in the high molecular weight fractions. According to the invention, polyethylene film made with the inventive copolymer has a balance of improved physical, optical, mechanical properties as well as processability. In one aspect, the film includes a 1% secant modulus of greater than 25,000 psi, a film haze of less than 10, a film clarity of greater than 90, a dart impart resistance of greater than 500 g/mil, and a MD tear strength of greater than 500 g/mil.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: April 9, 2024
    Assignee: Formosa Plastics Corporation, USA
    Inventors: Guangxue Xu, Zhiming Wang, Chih-Jian Chen, Honglan Lu
  • Publication number: 20240111337
    Abstract: An electronic device including a body and a receptacle connector is provided. The body has a side wall surface, a receptacle slot located at the side wall surface, a waterproof protrusion protruding from the side wall surface, and two gutters located at the side wall surface, where the waterproof protrusion is located above the receptacle slot, and the two gutters are respectively located at two opposite sides of the receptacle slot. The receptacle connector is disposed in the receptacle slot.
    Type: Application
    Filed: May 8, 2023
    Publication date: April 4, 2024
    Applicant: Acer Incorporated
    Inventors: Wei-Chih Wang, Chen-Min Hsiu, Chien-Yu Lee, Szu-Wei Yang, Fang-Ying Huang
  • Patent number: 11950222
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive a configuration that indicates multiple time intervals corresponding to multiple physical sidelink shared channels (PSSCHs) within a slot, wherein at least one PSSCH, of the multiple PSSCHs, starts in a symbol other than an initial data symbol of the slot. The UE may communicate in one or more PSSCHs, of the multiple PSSCHs, within the slot based at least in part on the configuration. Numerous other aspects are described.
    Type: Grant
    Filed: June 1, 2021
    Date of Patent: April 2, 2024
    Assignee: QUALCOMM Incorporated
    Inventors: Chih-Hao Liu, Yisheng Xue, Jing Sun, Xiaoxia Zhang, Tao Luo, Sony Akkarakaran, Xiaojie Wang, Lik Hang Silas Fong, Piyush Gupta
  • Patent number: 11949388
    Abstract: A power amplifier includes a power switching circuit, a driver circuit, and an amplifier circuit. The power switching circuit is configured to receive a first voltage and a second voltage, and provide the first voltage or the second voltage according to an operation mode of the power amplifier. The driver circuit is coupled to the power switching circuit. The driver circuit is configured to operate according to the first voltage or the second voltage and generate a driving signal according to an input signal. The amplifier circuit is coupled to the power switching circuit and the driver circuit. The amplifier circuit is configured to operate according to the first voltage or the second voltage and generate an output signal according to the driving signal.
    Type: Grant
    Filed: November 23, 2021
    Date of Patent: April 2, 2024
    Assignee: REALTEK SEMICONDUCTOR CORPORATION
    Inventors: Gen-Sheng Ran, Po-Chih Wang, Ka-Un Chan
  • Patent number: 11944870
    Abstract: The disclosure provides a movement determination method, a movement determination device, and a computer-readable storage medium. The method includes the following. In response to determining that a user has presented an initial movement corresponding to a to-be-detected movement, an anchor joint point among multiple joint points of the user is decided based on the to-be-detected movement. A movable range of each of the anchor joint points is decided. In response to determining that each of the anchor joint points leaves the corresponding movable range, it is determined that the user has stopped performing the to-be-detected movement.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: April 2, 2024
    Assignee: BOMDIC INC.
    Inventors: Leong Kian Tee, Haoyi Chih, En-Tzu Wang
  • Publication number: 20240107414
    Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for switching a secondary cell to a primary cell. A user equipment (UE) monitors a first radio condition of the UE for beams of a primary cell and a second radio condition for beams of one or more secondary cells configured for the UE in carrier aggregation. The UE transmits a request to configure a candidate beam of at least one candidate secondary cell as a new primary cell in response to the first radio condition not satisfying a first threshold and the second radio condition for the at least one candidate secondary cell satisfying a second threshold. A base station determines to reconfigure at least one secondary cell as the new primary cell. The base station and the UE perform a handover of the UE to the new primary cell.
    Type: Application
    Filed: September 23, 2022
    Publication date: March 28, 2024
    Inventors: Yu-Chieh HUANG, Kuhn-Chang LIN, Jen-Chun CHANG, Wen-Hsin HSIA, Chia-Jou LU, Sheng-Chih WANG, Chenghsin LIN, Yeong Leong CHOO, Chun-Hsiang CHIU, Chihhung HSIEH, Kai-Chun CHENG, Chung Wei LIN