Patents by Inventor Chih Wang

Chih Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240105480
    Abstract: A wafer storage elevator and method for detecting wafer position shift. The elevator includes a first storage elevator sidewall, a second storage elevator sidewall, and a storage seat positioned between the first and second storage elevator sidewalls. A first mirror block is coupled to a front side of the storage seat having a mirror positioned on a top surface of the block, and a second mirror block is coupled to the front side of the storage seat having a mirror that is positioned on the top surface of the second mirror block. The mirror of the first mirror block reflects a laser beam from an emission sensor to the second mirror block, and the mirror of the second mirror block reflects the laser beam from the mirror of the first mirror block to a receive sensor. A wafer misalignment is determined based upon an output of the receive sensor.
    Type: Application
    Filed: January 4, 2023
    Publication date: March 28, 2024
    Inventors: Ming-Sze Chen, Yuan-Hsin Chi, Hung-Chih Wang, Sheng-Yuan Lin
  • Patent number: 11942906
    Abstract: The present invention provides a transmitter including a mixer, a harmonic impedance adjustment circuit and an amplifier. The mixer is configured to mix a first baseband signal with a first oscillation signal to generate a first mixed signal to a first node, and to mix a second baseband signal with a second oscillation signal to generate a second mixed signal to a second node. The harmonic impedance adjustment circuit is coupled between the first node and the second node, and is configured to reduce harmonic components of the first mixed signal and the second mixed signal to generate an adjusted first mixed signal and an adjusted second mixed signal. The amplifier is coupled to the harmonic impedance adjustment circuit, and is configured to generate an amplified signal according to the adjusted first mixed signal and the adjusted second mixed signal.
    Type: Grant
    Filed: February 7, 2022
    Date of Patent: March 26, 2024
    Assignee: Realtek Semiconductor Corp.
    Inventors: Ting-Yao Huang, Teng-Yuan Chang, Po-Chih Wang, Ka-Un Chan
  • Patent number: 11939293
    Abstract: A novel compound selected from is disclosed.
    Type: Grant
    Filed: September 28, 2022
    Date of Patent: March 26, 2024
    Assignee: UNIVERSAL DISPLAY CORPORATION
    Inventors: Bin Ma, Ting-Chih Wang, Vadim Adamovich
  • Patent number: 11941741
    Abstract: A graphics system includes an effect engine and a graphics pipeline. The graphics pipeline performs pipeline operations on graphical objects in a frame. The graphics pipeline includes at least a fragment shader stage. An application programming interface (API) provides an instruction that specifies a subset of the graphical objects in the frame for the effect engine to execute. When detecting the instruction, the graphics pipeline invokes the effect engine to perform a predefined set of graphics operations on the subset of the graphical objects in the frame. The predefined set of graphics operations has a higher computational complexity than the pipeline operations.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: March 26, 2024
    Assignee: MediaTek Inc.
    Inventors: Chien-Chih Wang, Ying-Chieh Chen
  • Publication number: 20240084445
    Abstract: A leak check is performed on a semiconductor wafer processing tool that includes a process chamber and process gas lines, and a semiconductor wafer is processed using the semiconductor wafer processing tool if the leak check passes. Each gas line includes a mass flow controller (MFC) and normally closed valves including an upstream and downstream valves upstream and downstream of the MFC. Leak checking includes: leak checking up to the downstream valves of the gas lines with the upstream valves closed and the downstream valves of the gas lines closed; and leak checking up to the upstream valve of each the process gas line with the upstream valves of the of the process gas lines closed and with the downstream valve of the of the process gas line being leak checked open and the downstream valve of every other process gas line closed.
    Type: Application
    Filed: January 4, 2023
    Publication date: March 14, 2024
    Inventors: Chih-Wei Chou, Yuan-Hsin Chi, Chih-Hao Yang, Hung-Chih Wang, Yu-Chi Liu, Sheng-Yuan Lin
  • Publication number: 20240090314
    Abstract: Provided are organic light emitting devices (OLED) comprising an anode; a cathode, and an organic layer between the anode and the cathode, the organic layer comprising a light-emitting dopant within a host material, the light-emitting dopant being an optically active Pt complex comprising a tetradentate ligand; wherein one enantiomer of the optically active Pt complex is present in an enantiomeric excess (ee) of at least 5%. Further provided are OLEDs comprising an anode, a cathode, and an organic layer between the anode and the cathode, the organic layer the organic layer comprising a light-emitting chiral dopant within a chiral host material, the light-emitting chiral dopant being an optically active complex; wherein one enantiomer of the optically active complex of the chiral dopant is present in an ee of at least 5%, and wherein one enantiomer of the chiral host material is present in an ee of at least 5%.
    Type: Application
    Filed: July 14, 2023
    Publication date: March 14, 2024
    Applicant: UNIVERSAL DISPLAY CORPORATION
    Inventors: Ting-Chih WANG, Hsiao-Fan CHEN, Geza SZIGETHY, Joseph A. MACOR, Neil PALMER, Jerald FELDMAN, Jason BROOKS
  • Patent number: 11930630
    Abstract: A Dynamic Random Access Memory (DRAM) capacitor and a preparation method therefor are provided. The DRAM capacitor includes a dielectric layer, and the dielectric layer includes a high dielectric material layer, and low dielectric loss material layers provided on both side surfaces of the high dielectric material layer.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: March 12, 2024
    Assignee: CHANGXIN MEMORY TECHNOLOGIES, INC.
    Inventors: Zhuo Chen, Ying-Chih Wang, Shih-Shin Wang
  • Publication number: 20240068754
    Abstract: A heat dissipation module used for an electronic device is provided. The electronic device has a heat source. The heat dissipation module includes an evaporator, a plurality of heat conducting components, a pipe connected to the evaporator to form a loop, and a working fluid filled in the loop. An exterior of the evaporator has a heat conducting zone thermally contacted with the heat source to absorb heat generated from the heat source. The heat conducting components are disposed in the evaporator, located at an interior of the evaporator corresponding to the heat conducting zone. The heat conducting components are in pillar shape or rib shape respectively. The working fluid in liquid passes through the evaporator, absorbs heat, and is transformed into vapor to flow out of the evaporator. Each of the heat conducting components in rib shape is oriented in a flow direction of the working fluid.
    Type: Application
    Filed: November 9, 2023
    Publication date: February 29, 2024
    Applicant: Acer Incorporated
    Inventors: Yung-Chih Wang, Jau-Han Ke, Wen-Neng Liao, Cheng-Wen Hsieh
  • Patent number: 11915621
    Abstract: A label sticker is provided and includes: a base layer; a release layer coated on an upper surface of the base layer; a first surface material layer having a lower surface coated with a first glue layer and coated on or adhered to the release layer through the first glue layer; and a second surface material layer having a lower surface coated with a second glue layer and adhered to an upper surface of the first surface material layer through the second glue layer. The area of the second surface material layer is greater than the area of the first surface material layer. The label sticker. Therefore, glue residues left behind by a process of making the label sticker do not interfere with use thereof.
    Type: Grant
    Filed: September 14, 2021
    Date of Patent: February 27, 2024
    Inventor: Chin-Chih Wang Tsai
  • Publication number: 20240059515
    Abstract: A cardboard conveyor device forms sub negative pressure regions communicative to a main negative pressure region by using wind shield structures of a plate body structure, thus saving power consumption of an aspirator. The plate body structure is for example formed by three plate bodies, the plate body of a middle layer has air holes, the plate body of an upper layer has first interval spaces penetrating the plate body of the upper layer, and the plate body of a lower layer has second interval spaces penetrating the plate body of the lower layer. Each of the first interval spaces is communicative to the corresponding second interval space via the corresponding air holes, and the second interval spaces are communicative to the main negative pressure region. Thus, the sub negative pressure regions can provide a negative pressure to the cardboard being conveyed.
    Type: Application
    Filed: October 19, 2022
    Publication date: February 22, 2024
    Inventor: CHIH-WANG CHEN
  • Publication number: 20240048965
    Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, from a network node, a network assistant information (NAI) message identifying a set of characteristics of a network connection. The UE may communicate with the network node using a communication configuration associated with the set of characteristics of the network connection. Numerous other aspects are described.
    Type: Application
    Filed: August 4, 2022
    Publication date: February 8, 2024
    Inventors: Kai-Chun CHENG, Jen-Chun CHANG, Kuhn-Chang LIN, Wen-Hsin HSIA, Chia-Jou LU, Sheng-Chih WANG, Chenghsin LIN, Yu-Chieh HUANG, Chun-Hsiang CHIU, ChihHung HSIEH, Chung Wei LIN, Yeong Leong CHOO
  • Publication number: 20240043710
    Abstract: A conductive ink may include an ultraviolet-curable resin and high-aspect-ratio conductors, such as nanowires or carbon nanotubes, dispersed in the ultraviolet-curable resin. The conductive ink may be fully curable at room temperature in under a minute with a curing depth of at least 100 microns, without heat, moisture, or a secondary curing step. The conductive ink may also have pigment and/or dyes within the ultraviolet-curable resin, and the conductive ink may be opaque at infrared wavelengths and transparent at ultraviolet wavelengths. The conductive ink may ground the cover glass of an electronic device display to a metal structure within the electronic device, such as a metal plate of the display, to prevent an accumulation of charge at the cover glass.
    Type: Application
    Filed: October 24, 2022
    Publication date: February 8, 2024
    Inventors: Ken Hsuan Liao, Ying-Chih Wang, Shu Yang, Yu-Jen Fang, Po-Jui Chen, Andrew H Moon, Sarah Trabia, Nathan K Gupta
  • Publication number: 20240038741
    Abstract: A package structure includes a package substrate, a first die, a second die, a first underfill, and a second underfill. The first die and a second die are disposed on the package substrate. The first underfill is between the first die and the package substrate, and the first underfill includes a first extension portion extending from a first sidewall of the first die toward the second die. The second underfill is between the second die and the package substrate, and the second underfill includes a second extension portion extending from a second sidewall of the second die toward the first die, the second extension portion overlapping the first extension portion on the package substrate.
    Type: Application
    Filed: October 6, 2023
    Publication date: February 1, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jen-Yuan CHANG, Sheng-Chih WANG
  • Patent number: 11889645
    Abstract: A foldable electronic device includes a first casing, a second casing, a hinge structure and a foldable display. The hinge structure connects the first casing and the second casing, and includes a plurality of supporting blocks, a plurality of first hinge blocks and a plurality of second hinge blocks. The supporting blocks are arranged side by side between the first casing and the second casing. The first hinge blocks and the second hinge blocks are respectively arranged at two sides of the supporting blocks. One of the first hinge blocks connects two of the supporting blocks adjacent to each other. One of the second hinge blocks connects two of the supporting blocks adjacent to each other. The foldable display includes a first bonding portion secured to the first casing, a second bonding portion secured to the second casing and a foldable portion aligned to the hinge structure.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: January 30, 2024
    Assignee: Acer Incorporated
    Inventors: Hui-Ping Sun, Wei-Chih Wang, Chun-Hung Wen, Yu-Cheng Shih, Yen-Chou Chueh, Chi-Tai Ho, Kuan-Lin Chen, Chun-Hsien Chen, Chih-Heng Tsou
  • Patent number: 11889647
    Abstract: An electronic device includes a housing that defines an aperture, and a display assembly positioned in the aperture. The display assembly can include a display layer having a first portion, and a second portion bending at least partially below the first portion. The first portion and the second portion can define a bend volume, and a potting material can be disposed in the bend volume, such that the potting material contacts the first portion and the second portion. An internal enclosure can be contoured to the display assembly.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: January 30, 2024
    Assignee: APPLE INC.
    Inventors: Izhar Z. Ahmed, John J. Baker, Bulong Wu, Daniel W. Jarvis, Douglas G. Fournier, Eric W. Bates, Hao Dong, Isabel S Gueble, Jason C. Law, Jingjing Xu, Kikue S. Burnham, Paul U. Leutheuser, Sarah Trabia, Sawyer I. Cohen, Shaorui Yang, Shaowei Qin, Siddharth Avachat, Yaocheng Zhang, Ying-Chih Wang, Zhen Zhang, Benjamin R. Pope
  • Publication number: 20240021416
    Abstract: A connect structure for semiconductor processing equipment includes a housing configured to mate a deformable pipe with a non-deformable pipe. The housing includes a first annular sidewall to receive the deformable pipe and a second annular sidewall defining a first thread structure. An annular bead is connected to the first annular sidewall to flexibly deform the deformable pipe toward the non-deformable pipe structure when the first thread structure rotatably engages a second thread structure of the non-deformable pipe.
    Type: Application
    Filed: July 18, 2022
    Publication date: January 18, 2024
    Inventors: Ming-Sze Chen, Hung-Chih Wang, Yuan-Hsin Chi, Sheng-Yuan Lin
  • Patent number: 11875181
    Abstract: A management controller is coupled to a plurality of external devices. The management controller includes a control circuit and a transmission circuit. The control circuit generates a control signal according to a first counting value and a second counting value. The transmission circuit is coupled to the external devices. In response to the first counting value not being equal to a first target value, the transmission circuit enters a circulating mode according to the control signal. In the circulating mode, the transmission circuit triggers the external devices in order. In response to the second counting value not being equal to a second target value, the transmission circuit continues to operate in the circulating mode. In response to the second counting value being equal to the second target value, the transmission circuit exits the circulating mode.
    Type: Grant
    Filed: December 29, 2020
    Date of Patent: January 16, 2024
    Assignee: NUVOTON TECHNOLOGY CORPORATION
    Inventor: Cheng-Chih Wang
  • Patent number: 11860394
    Abstract: An electronic device may have a display overlapped by an image transport layer such as a coherent fiber bundle or layer of Anderson localization material. The image transport layer may have an input surface that receives an image from the display and a corresponding output surface to which the image is transported. The input surface and output surface may have different shapes. During fabrication of the image transport layer, molding techniques, grinding and polishing techniques, and other processes may be used to deform the image transport layer and the shape of the output surface. To help reduce ambient light reflections and stray light, light-absorbing structures may be incorporated into the image transport layer and other structures overlapping the display.
    Type: Grant
    Filed: July 21, 2020
    Date of Patent: January 2, 2024
    Assignee: Apple Inc.
    Inventors: Yi Qiao, Jean-Pierre S. Guillou, Michael J. Brown, Paul C. Kelley, Tyler R. Kakuda, Ying-Chih Wang, Salman Karbasi
  • Patent number: 11852420
    Abstract: A heat dissipation module used for an electronic device is provided. The electronic device has a heat source. The heat dissipation module includes an evaporator, a pipe, and a working fluid. The evaporator has a recess at an exterior surface thereof, and is thermally contacted with the heat source to absorb heat generated from the heat source. The pipe is connected to an inner space of the evaporator and forms a loop. The working fluid is filled in the loop, wherein the working fluid in liquid passes through the evaporator, absorbs heat, and is transformed into vapor to flow out of the evaporator.
    Type: Grant
    Filed: February 15, 2023
    Date of Patent: December 26, 2023
    Assignee: Acer Incorporated
    Inventors: Yung-Chih Wang, Jau-Han Ke, Wen-Neng Liao, Cheng-Wen Hsieh
  • Publication number: 20230402740
    Abstract: A Duo Aloe Vera Cruces Concentricis antenna structure is provided and includes a first conductive layer, a dielectric layer and a second conductive layer. The first metal units of the first conductive layer form a first tapered hole, The second metal units of the first conductive layer are located in the first tapered hole and form a second tapered hole. The third metal units and the fourth metal units of the dielectric layer are aligned with the first metal units and the second metal units, respectively. The second conductive layer is connected to the dielectric layer. The first tapered hole has at least one first center line. The second tapered hole has at least one second center line. An included angle between the at least one first center line and the at least one second center line is 45 degrees.
    Type: Application
    Filed: June 9, 2022
    Publication date: December 14, 2023
    Applicant: National Tsing Hua University
    Inventors: Wei-Chih Wang, Prabir Garu, Fiona Marie Wang