Abstract: A capacitor structure including a substrate, at least one first dielectric layer, at least one second dielectric layer, a capacitor, and an interconnect structure is provided. The substrate includes a capacitor region and a non-capacitor region. The first dielectric layer is located in the capacitor region and the non-capacitor region. The second dielectric layer is located in the non-capacitor region. At least a portion of the second dielectric layer is located in the first dielectric layer. A material of the second dielectric layer is different from a material of at least a portion of the first dielectric layer. A dielectric constant of the second dielectric layer is smaller than a dielectric constant of at least a portion of the first dielectric layer. The capacitor is located in the first dielectric layer in the capacitor region. The interconnect structure is located in the second dielectric layer in the non-capacitor region.

Abstract: Devices and methods for controlling wafer uniformity using a gas baffle plate are disclosed. In one example, a device for plasma-based processes is disclosed. The device includes: a housing defining a process chamber and a baffle plate arranged above a wafer in the process chamber. The baffle plate is configured to control plasma distribution on the wafer. The baffle plate has a shape of an annulus that comprises a first annulus sector and a second annulus sector. The first annulus sector has a first inner radius. The second annulus sector has a second inner radius that is different from the first inner radius.

Abstract: An image sensor module comprises an image sensor having a light sensing area, a cover glass for covering the light sensing area, a dam between the image sensor and the cover glass, which surrounds the light sensing area, and has an outer wall and an inner wall, where a cross-section of the inner wall parallel to the surface of the light sensing area of the image sensor forms a sawtooth pattern and/or, where a cross-section of the inner wall orthogonal to the surface of the light sensing area of the image sensor forms an inclined surface.

Abstract: An electronic apparatus, a semiconductor package module and a method for manufacturing the semiconductor package module are provided. The semiconductor package module includes: an encapsulated structure, including a device die and an encapsulant laterally enclosing the device die; a package substrate, attached to a first side of the encapsulated structure; a composite thermal interfacial structure, disposed on a second side of the encapsulated structure, and including thermally conductive elements arranged side by side or stacked along a vertical direction; a ring structure, attached to the package substrate and laterally surrounding the encapsulated structure; and a heat spreader, attached to the second side of the encapsulated structure through the composite thermal interfacial structure, and supported by the ring structure.

Abstract: A semiconductor package includes a first heat dissipation plate, a second heat dissipation plate, a plurality of heat generating assemblies, and a plurality of fixture components. The first heat dissipation plate has a first upper surface and a first lower surface. The first heat dissipation plate includes first through holes extended from the first upper surface to the first lower surface. The second heat dissipation plate has a second upper surface and a second lower surface. The second heat dissipation plate includes second through holes extended from the second upper surface to the second lower surface. The heat generating assemblies are disposed between the first heat dissipation plate and the second heat dissipation plate. The fixture components include fix screws and nuts. The fix screws penetrate through the first heat dissipation plate and the second heat dissipation plate along the first through holes and the second through holes.

Abstract: A semiconductor device includes a vapor chamber lid for high power applications such as chip-on-wafer-on-substrate (CoWoS) applications using high performance processors (e.g., graphics processing unit (GPU)) and methods of manufacturing the same. The vapor chamber lid provides a thermal solution which enhances the thermal performance of a package with multiple chips. The vapor chamber lid improves hot spot dissipation in high performance chips, for example, at the three-dimensional (3D-IC) packaging level.

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a substrate, a die stack disposed over the substrate, a heat spreader disposed over the substrate and having a surface facing the substrate, and a thermal interface material (TIM) disposed between the die stack and the heat spreader. A bottommost die of the die stack includes a surface exposed from remaining dies of the die stack from a top view perspective; and the TIM is in contact with the exposed surface of the bottommost die and the surface of the heat spreader, and is in contact with a sidewall of at least one of the plurality of dies of the die stack.

Abstract: The invention relates to crystalline forms of the bis-HCl salt of a compound represented by Structural Formula 1, and pharmaceutical compositions comprising crystalline forms of the bis-HCL salt of a compound represented by Structural Formula 1 described herein. The crystalline forms of the bis-HCl salt of a compound of Structural Formula 1 and compositions comprising the crystalline forms of the compound of Structural Formula 1 provided herein, in particular, crystalline Form I, crystalline Form J, crystalline Form A, and crystalline Form B, or mixtures thereof, can be incorporated into pharmaceutical compositions, which can be used to treat various disorders. Also described herein are methods for preparing the crystalline forms (e.g., Forms I, J, B and A) of the bis-HCl salt of a compound represented by Structural Formula 1.

Abstract: The disclosure provides a voltage adjust circuit. The voltage adjust circuit includes a buffer circuit, a bias circuit, a level shifter and a cross voltage limit circuit. The buffer circuit includes a plurality of pull-up transistors and a plurality of pull-down transistors. The pull-up transistors coupled in series between an output terminal of the circuit and a high voltage system terminal. The pull-down transistors coupled in series between the output terminal and a low voltage system terminal. The cross voltage limit circuit is configured to limit transient and static bias voltages across two terminals of the pull-up transistors or the pull-down transistors.

Abstract: A wavelength converting includes a diffused-reflecting layer, a substrate, a photoluminescence layer, and a binder. The diffused-reflecting layer has a first surface and a second surface facing away from each other. The substrate is over the first surface of the diffused-reflecting layer. The photoluminescence layer is over the second surface of the diffused-reflecting layer. The binder is mixed at least in the photoluminescence layer or at least in the diffused-reflecting layer, the binder includes a structural unit represented by formula (1), and a characteristic absorption band in a Fourier-Transform Infrared (FTIR) Spectrum of silicon-oxygen-silicon bonds (Si—O—Si bonds) in the binder is from 900 cm?1 to 1250 cm?1, in which R represents an aromatic group.

Abstract: A wavelength conversion device includes a wavelength conversion plate, a reflective layer, a driving component and a thermal conductive layer. The wavelength conversion plate includes a lateral edge, at least one surface and a conversion region. The reflective layer is disposed on the surface of the wavelength conversion plate. The driving component is disposed near the lateral edge of the wavelength conversion plate and configured to displace the wavelength conversion plate. The thermal conductive layer is disposed on the surface of the wavelength conversion plate and thermally connected to the conversion region for conducting heat generated by the conversion region during a wavelength conversion. By disposing the thermal conductive layer on the surface of the wavelength conversion plate, the thermal conductive layer is thermally directly connected to the conversion region, so that the heat generated at the conversion region during the wavelength conversion is efficiently dissipated.

Abstract: A wavelength conversion device includes a substrate, a reflective layer, a phosphor layer and a thermal conductive layer. The substrate has a surface. The reflective layer is disposed on the surface of the substrate. The phosphor layer is disposed on the reflective layer and has a conversion region configured to perform a wavelength conversion. The thermal conductive layer is disposed on the surface of the substrate and thermally directly connected to the conversion region for conducting a heat generated at the conversion region during the wavelength conversion. The thermal resistance of the reflective layer is high and causes heat in the conversion region to accumulate. By disposing the thermal conductive layer adjacent to a side of the phosphor layer, the thermal conductive layer is thermally directly connected to the conversion region, so that the heat generated at the conversion region during the wavelength conversion is efficiently dissipated.

Abstract: An aspect relates to an apparatus including an input buffer including an input configured to receive an input voltage; a ramp voltage generator including an input coupled to an output of the input buffer; an evaluation circuit including an input coupled to an output of the ramp voltage generator, wherein the evaluation circuit includes a first resistor coupled in series with first field effect transistor (FET) between a first voltage rail and a second voltage rail; and an output buffer including an input coupled to a drain of the first FET and an output configured to generate an output voltage.

Abstract: A layout method includes disposing a first conductive path and a second conductive path across a boundary between a first layout device and a second layout device abutting the first layout device. The layout method also includes disposing a first cut layer on the first conductive path nearby the boundary, and disposing a second cut layer on the second conductive path nearby the boundary. The layout method also includes moving the first cut layer to align with the second cut layer.

Abstract: An image sensor module comprises an image sensor having a light sensing area, a cover glass for covering the light sensing area, a dam between the image sensor and the cover glass, which surrounds the light sensing area, and has an outer wall and an inner wall, where a cross-section of the inner wall parallel to the surface of the light sensing area of the image sensor forms a sawtooth pattern and/or, where a cross-section of the inner wall orthogonal to the surface of the light sensing area of the image sensor forms an inclined surface.

Abstract: A semiconductor device includes a semiconductor substrate, a first gate oxide layer, and a first source/drain doped region. The first gate oxide layer is disposed on the semiconductor substrate, and the first gate oxide layer includes a main portion and an edge portion having a sloping sidewall. The first source/drain doped region is disposed in the semiconductor substrate and located adjacent to the edge portion of the first gate oxide layer. The first source/drain doped region includes a first portion and a second portion. The first portion is disposed under the edge portion of the first gate oxide layer in a vertical direction, and the second portion is connected with the first portion.

Abstract: A level shifter includes a buffer circuit, a first shift circuit, and a second shift circuit. The buffer circuit provides a first signal and a first inverted signal to the first shift circuit, such that the first shift circuit provides a second signal and a second inverted signal to the second shift circuit. The second shift circuit generates a plurality of output signals according to the second signal and the second inverted signal. The first shift circuit includes a plurality of first stacking transistors and a first voltage divider circuit. The first voltage divider circuit is electrically coupled between a first system high voltage terminal and a system low voltage terminal. The first voltage divider circuit is configured to provide a first inner bias to gate terminals of the first stacking transistors.

Abstract: The disclosure provides a voltage adjust circuit. The voltage adjust circuit includes a buffer circuit, a bias circuit, a level shifter and a cross voltage limit circuit. The buffer circuit includes a plurality of pull-up transistors and a plurality of pull-down transistors. The pull-up transistors coupled in series between an output terminal of the circuit and a high voltage system terminal. The pull-down transistors coupled in series between the output terminal and a low voltage system terminal. The cross voltage limit circuit is configured to limit transient and static bias voltages across two terminals of the pull-up transistors or the pull-down transistors.

Abstract: Devices and methods for controlling wafer uniformity using a gas baffle plate are disclosed. In one example, a device for plasma-based processes is disclosed. The device includes: a housing defining a process chamber and a baffle plate arranged above a wafer in the process chamber. The baffle plate is configured to control plasma distribution on the wafer. The baffle plate has a shape of an annulus that comprises a first annulus sector and a second annulus sector. The first annulus sector has a first inner radius. The second annulus sector has a second inner radius that is different from the first inner radius.

Abstract: Devices and methods for controlling wafer uniformity in plasma-based process is disclosed. In one example, a device for plasma-based processes is disclosed. The device includes: a housing defining a process chamber and a gas distribution plate (GDP) arranged in the process chamber. The housing comprises: a gas inlet configured to receive a process gas, and a gas outlet configured to expel processed gas. The GDP is configured to distribute the process gas within the process chamber. The GDP has a plurality of holes evenly distributed thereon. The GDP comprises a first zone and a second zone. The first zone is closer to the gas outlet than the second zone. At least one hole in the first zone is closed.