Abstract: A method for manufacturing a high efficiency light-emitting diode (LED) is disclosed. In the method, a substrate is provided, in which an N-type buffer layer, an N-type cladding layer and an active layer are stacked on the substrate in sequence. A first P-type cladding layer is formed on the active layer. Next, a growth-interruption step is performed, and a catalyst is introduced to form a plurality of nuclei sites on a surface of the first P-type cladding layer. A second P-type cladding layer is formed on the first P-type cladding layer according to the nuclei sites, so that the second P-type cladding layer has a surface with a plurality of mesa hillocks. Then, a contact layer is formed on the second P-type cladding layer. Subsequently, a transparent electrode is formed on the contact layer.

Abstract: Features of a mask, when close enough to one another, can cause unwanted phantom images to print on an integrated circuit. Advantageously, potential locations of phantom images can be automatically identified from a mask layout. This technique can include creating perimeters or rings around features in the mask layout (in one case, after proximity correction). An overlap of perimeters/rings can be assigned a particular weight such that areas of greater overlap have a higher weight and areas of less overlap have a lower weight. If the weight of an overlap area exceeds a trigger weight, then an evaluation point can be added to the mask layout, thereby identifying that layout location as a potential location of a phantom image. After simulation of the mask layout, that layout location can be analyzed to determine if a phantom image would print.

Abstract: Systems and methods are provided for programming and running simulation engines of lithographic simulations on GPUs. This integration of lithographic simulations includes the hosting on one or more GPUs of any of a variety of lithographic techniques, including for example resolution enhancement technologies, optical proximity correction, optical rule-checking or lithography checking, and model-based DRC, where operations of one or more techniques are run in parallel. The systems and methods provided also include the integration of lithographic geometry operations into GPUs to obtain improved performance. Examples of this integration include a Design Rule Checker (DRC), parasitic extraction, and placement and route for example.

Abstract: A method of generating simulation reports regarding an integrated circuit layout is provided. The method can include providing a plurality of control points associated with the integrated circuit layout. A single simulation of the plurality of control points can be performed. Detailed information from the single simulation can be stored in a database. Desired information can then be extracted from the database to generate the simulation reports.

Abstract: A method for manufacturing a high efficiency light-emitting diode (LED) is disclosed. In the method, a substrate is provided, in which an N-type buffer layer, an N-type cladding layer and an active layer are stacked on the substrate in sequence. A first P-type cladding layer is formed on the active layer. Next, a growth-interruption step is performed, and a catalyst is introduced to form a plurality of nuclei sites on a surface of the first P-type cladding layer. A second P-type cladding layer is formed on the first P-type cladding layer according to the nuclei sites, so that the second P-type cladding layer has a surface with a plurality of mesa hillocks. Then, a contact layer is formed on the second P-type cladding layer. Subsequently, a transparent electrode is formed on the contact layer.

Abstract: A Wafer Image Modeling and Prediction System (“WIMAPS”) is described that includes systems and methods that generate and/or apply models of resolution enhancement techniques (“RET”) and printing processes in integrated circuit (“IC”) fabrication.

Abstract: A lithography mask layout is designed and verified incrementally to help reduce the amount of time to produce the mask layout. For one embodiment, a layout defining a target pattern may be processed to produce a mask layout, and the mask layout may be verified to identify errors. Rather than processing and verifying the entire mask layout for error correction over one or more subsequent iterations, sub-layouts having errors may be removed or copied from the mask layout for separate processing and verification. Because the amount of data defining a sub-layout is relatively small, the time to design and verify the mask layout is reduced. The resulting mask layout having one or more processed and verified sub-layout(s) may then be used to manufacture a mask set to help print the target pattern in manufacturing integrated circuits (ICs), for example.

Abstract: A lithography mask layout is designed and verified incrementally to help reduce the amount of time to produce the mask layout. For one embodiment, a layout defining a target pattern may be processed to produce a mask layout, and the mask layout may be verified to identify errors. Rather than processing and verifying the entire mask layout for error correction over one or more subsequent iterations, sub-layouts having errors may be removed or copied from the mask layout for separate processing and verification. Because the amount of data defining a sub-layout is relatively small, the time to design and verify the mask layout is reduced. The resulting mask layout having one or more processed and verified sub-layout(s) may then be used to manufacture a mask set to help print the target pattern in manufacturing integrated circuits (ICs), for example.

Abstract: Features of a mask, when close enough to one another, can cause unwanted phantom images to print on an integrated circuit. Advantageously, potential locations of phantom images can be automatically identified from a mask layout. This technique can include creating perimeters or rings around features in the mask layout (in one case, after proximity correction). An overlap of perimeters/rings can be assigned a particular weight such that areas of greater overlap have a higher weight and areas of less overlap have a lower weight. If the weight of an overlap area exceeds a trigger weight, then an evaluation point can be added to the mask layout, thereby identifying that layout location as a potential location of a phantom image. After simulation of the mask layout, that layout location can be analyzed to determine if a phantom image would print.

Abstract: A rotary dryer. The dryer includes a rotary drum and a dehumidifier. the rotary cylinder receives dry air and wet material, wherein The wet material is rotated by the rotary drum to completely contact the dry air so that The wet material changes to grains. the dehumidifier receives wet air from the rotary drum, dehumidifies the wet air, and introduces dry air to the rotary cylinder.

Abstract: A method and system of determining a sensitivity of an edge of a feature to mask error can be advantageously provided using information from multiple simulations. Input data as well as revised data regarding the edge can be used, wherein the revised data includes a first mask error. The input data can be simulated to generate first deviation information, whereas the revised data can be simulated to generate second deviation information accounting for the first mask error. The sensitivity of the edge to mask error can be generated using the first deviation information, the second deviation information, and the first mask error. Specifically, generating the sensitivity can include subtracting the first deviation information from the second deviation and dividing the difference by the first mask error.

Abstract: A method of generating simulation reports regarding an integrated circuit layout is provided. The method can include providing a plurality of control points associated with the integrated circuit layout. A single simulation of the plurality of control points can be performed. Detailed information from the single simulation can be stored in a database. Desired information can then be extracted from the database to generate the simulation reports.

Abstract: The quality of spiral images depends on whether actual k-space sampling points are at their nominal positions. Although newer gradient systems can provide more accurate gradient waveforms, timing mis-registration between data acquisition and gradient systems can significantly distort the positions of samples. Even after the timing of data acquisition is tuned, minor residual errors can still cause shading artifacts which are problematic for quantitative MRI applications, such as the phase-contrast method. Although ideally measuring the actual k-space trajectory can correct for the timing errors, it requires additional data acquisition and scan time. The present invention employs off-centered spiral trajectories which are more robust against timing errors and applies them to the phase-contrast method. The new trajectories turn shading artifacts into a slowly-varying linear phase in reconstructed images without affecting the magnitude of images.