Abstract: The present disclosure describes a device that is protected from the effects of an oxide on the metal gate layers of ferroelectric field effect transistors.

Abstract: A method includes forming a dummy gate stack on a semiconductor region, forming gate spacers on sidewalls of the dummy gate stack, removing the dummy gate stack to form a recess between the gate spacers, and forming a silicon oxide layer on the semiconductor region. The silicon oxide layer extends into the recess. A high-k dielectric layer is deposited over the silicon oxide layer, and a silicon layer is deposited over the high-k dielectric layer. The silicon layer extends into the recess. The high-k dielectric layer and the silicon layer are in-situ deposited in a same vacuum environment. The method further includes performing an annealing process on the silicon layer and the high-k dielectric layer, removing the silicon layer, and forming a gate electrode over the high-k dielectric layer. The gate electrode fills the recess.

Abstract: Embodiments provide an integrated capacitor disposed directly over and aligned to a vertical gate all around memory cell transistor. In some embodiments, an air gap may be provided between adjacent word lines to provide a low k dielectric effect between word lines. In some embodiments, a bottom bitline structure may be split across multiple layers. In some embodiments, a second tier of vertical cells may be positioned over a first tier of vertical cells.

Abstract: The present disclosure provides embodiments of semiconductor structures and method of forming the same. An example semiconductor structure includes a first source/drain feature and a second source/drain feature and a hybrid fin disposed between the first source/drain feature and the second source/drain feature and extending lengthwise along a first direction. The hybrid fin includes an inner feature and an outer layer disposed around the inner feature. The outer layer includes silicon oxycarbonitride and the inner feature includes silicon carbonitride.

Abstract: A nano-crystalline high-k film and methods of forming the same in a semiconductor device are disclosed herein. The nano-crystalline high-k film may be initially deposited as an amorphous matrix layer of dielectric material and self-contained nano-crystallite regions may be formed within and suspended in the amorphous matrix layer. As such, the amorphous matrix layer material separates the self-contained nano-crystallite regions from one another preventing grain boundaries from forming as leakage and/or oxidant paths within the dielectric layer. Dopants may be implanted in the dielectric material and crystal phase of the self-contained nano-crystallite regions maybe modified to change one or more of the permittivity of the high-k dielectric material and/or a ferroelectric property of the dielectric material.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate over a fin, where the fin protrudes above a substrate; surrounding the dummy gate with a dielectric material; and replacing the dummy gate with a replacement gate structure, where replacing the dummy gate includes: forming a gate trench in the dielectric material, where forming the gate trench includes removing the dummy gate; forming a metal-gate stack in the gate trench, where forming the metal-gate stack includes forming a gate dielectric layer, a first work function layer, and a gap-filling material sequentially in the gate trench; and enlarging a volume of the gap-filling material in the gate trench.

Abstract: A semiconductor device including a substrate, a first transistor and a second transistor is provided. The first transistor includes a first gate structure over the first semiconductor fin. The first gate structure includes a first high-k layer and a first work function layer sequentially disposed on the substrate, a material of the first work function layer may include metal carbide and aluminum, and a content of aluminum in the first work function layer is less than 10% atm. The second transistor includes a second gate structure. The second gate structure includes a second high-k layer and a second work function layer sequentially disposed on the substrate. A work function of the first work function layer is greater than a work function of the second work function layer.

Abstract: An embodiment includes a device including a first high-k gate dielectric on a first channel region of a first semiconductor feature, the first high-k gate dielectric being a crystalline layer with a grain size in a range of 10 ? to 200 ?. The device also includes a first gate electrode on the first high-k gate dielectric. The device also includes a source region and a drain region on opposite sides of the first gate electrode.

Abstract: In method of manufacturing a semiconductor device, an opening is formed over a first conductive layer in a dielectric layer, a second conductive layer is formed over the first conductive layer in the opening without forming the second conductive layer on at least an upper surface of the dielectric layer, a third conductive layer is formed over the second conductive layer in the opening without forming the third conductive layer on at least an upper surface of the dielectric layer, and an upper layer is formed over the third conductive layer in the opening.

Abstract: Embodiments utilize an electro-chemical process to deposit a metal gate electrode in a gate opening in a gate replacement process for a nanosheet FinFET device. Accelerators and suppressors may be used to achieve a bottom-up deposition for a fill material of the metal gate electrode.

Abstract: The present disclosure relates to a semiconductor device including a substrate and first and second spacers on the substrate. The semiconductor device also includes a gate stack between the first and second spacers. The gate stack includes a gate dielectric layer having a first portion formed on the substrate and a second portion formed on the first and second spacers; an internal gate formed on the first and second portions of the gate dielectric layer; a ferroelectric dielectric layer formed on the internal gate and in contact with the gate dielectric layer; and a gate electrode on the ferroelectric dielectric layer.

Abstract: A semiconductor device a method of forming the same are provided. The method includes forming a fin extending from a substrate. A dummy gate is formed over the fin. The dummy gate extends along sidewalls and a top surface of the fin. The dummy gate is removed to form a recess. A replacement gate is formed in the recess. Forming the replacement gate includes forming an interfacial layer along sidewalls and a bottom of the recess. A dipole layer is formed over the interfacial layer. The dipole layer includes metal atoms. Fluorine atoms are incorporated in the dipole layer. The fluorine atoms and the metal atoms are driven from the dipole layer into the interfacial layer. The dipole layer is removed.

Abstract: A method of forming a semiconductor device including forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, the first semiconductor layers and the second semiconductor layers having different compositions, forming a dummy gate structure across the fin structure, forming gate spacers on opposite sidewalls of the dummy gate structure, respectively, removing the dummy gate structure to form a gate trench between the gate spacers, etching the first semiconductor layers in the gate trench, such that the second semiconductor layers are suspended in the gate trench to serve as nanosheets, forming a work function metal layer surrounding each of the nanosheets, and depositing a fill metal layer over the work function metal layer without using a fluorine-containing precursor.

Abstract: A structure and formation method of a semiconductor device is provided. The semiconductor device structure includes an epitaxial structure over a semiconductor substrate. The semiconductor device structure also includes a dielectric fin over the semiconductor substrate. The dielectric fin extends upwards to exceed a bottom surface of the epitaxial structure. The dielectric fin has a dielectric structure and a protective shell, and the protective shell extends along sidewalls and a bottom of the dielectric structure. The protective shell has a first average grain size, and the dielectric structure has a second average grain size. The first average grain size is larger than the second average grain size.

Abstract: In an embodiment, a device includes: a first channel region; a second channel region; and a gate structure around the first channel region and the second channel region, the gate structure including: a gate dielectric layer; a first p-type work function metal on the gate dielectric layer, the first p-type work function metal including fluorine and aluminum; a second p-type work function metal on the first p-type work function metal, the second p-type work function metal having a lower concentration of fluorine and a lower concentration of aluminum than the first p-type work function metal; and a fill layer on the second p-type work function metal.

Abstract: In an embodiment, a device includes: a first nanostructure over a substrate, the first nanostructure including a channel region and a first lightly doped source/drain region, the first lightly doped source/drain region adjacent the channel region; a first epitaxial source/drain region wrapped around four sides of the first lightly doped source/drain region; an interlayer dielectric over the first epitaxial source/drain region; a source/drain contact extending through the interlayer dielectric, the source/drain contact wrapped around four sides of the first epitaxial source/drain region; and a gate stack adjacent the source/drain contact and the first epitaxial source/drain region, the gate stack wrapped around four sides of the channel region.

Abstract: Semiconductor devices and methods of manufacture are presented in which spacers are manufactured on sidewalls of gates for semiconductor devices. In embodiments the spacers comprise a first seal, a second seal, and a contact etch stop layer, in which the first seal comprises a first shell along with a first bulk material, the second seal comprises a second shell along with a second bulk material, and the contact etch stop layer comprises a third bulk material and a second dielectric material.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate, the gate structure being surrounded by a first interlayer dielectric (ILD) layer; forming a trench in the first ILD layer adjacent to the fin; filling the trench with a first dummy material; forming a second ILD layer over the first ILD layer and the first dummy material; forming an opening in the first ILD layer and the second ILD layer, the opening exposing a sidewall of the first dummy material; lining sidewalls of the opening with a second dummy material; after the lining, forming a conductive material in the opening; after forming the conductive material, removing the first and the second dummy materials from the trench and the opening, respectively; and after the removing, sealing the opening and the trench by forming a dielectric layer over the second ILD layer.

Abstract: In an embodiment, a semiconductor device includes a first channel region disposed in a first device region over a substrate; a first gate dielectric layer disposed over the first channel region; and a gate electrode disposed over the first gate dielectric layer. The first gate dielectric layer includes a first dipole dopant and a second dipole dopant. The first dipole dopant along a thickness direction of the first gate dielectric layer has a first concentration peak, and the second dipole dopant along the thickness direction of the first gate dielectric layer has a second concentration peak. The second concentration peak is located between the first concentration peak and an upper surface of the first gate dielectric layer. The second concentration peak is offset from the upper surface of the first gate dielectric layer.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate having a base and a fin over the base. The semiconductor device structure also includes a first nanostructure over the fin and a second nanostructure over the first nanostructure. The semiconductor device structure further includes a gate stack wrapping around an upper portion of the fin, the first nanostructure, and the second nanostructure. In addition, the semiconductor device structure includes a first inner spacer between the fin and the first nanostructure and a second inner spacer between the first nanostructure and the second nanostructure. The semiconductor device structure includes a first low dielectric constant structure in the first inner spacer and a second low dielectric constant structure in the second inner spacer. The first low dielectric constant structure is larger than the second low dielectric constant structure.