Abstract: A method includes forming a dummy gate stack over a semiconductor region, forming a source/drain region on a side of the dummy gate stack, removing the dummy gate stack to form a trench, forming a gate dielectric layer extending into the trench and on the semiconductor region, and depositing a fist work-function layer over the gate dielectric layer. The work-function layer comprises a metal selected from the group consisting of ruthenium, molybdenum, and combinations thereof. The method further includes depositing a conductive filling layer over the first work-function layer, and performing a planarization process to remove excess portions of the conductive filling layer, the first work-function layer, and the gate dielectric layer to form a gate stack.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first fin structure and a second fin structure over a semiconductor substrate and a first epitaxial structure over the first fin structure. The semiconductor device structure also includes a second epitaxial structure over the second fin structure. The semiconductor device structure further includes a dielectric fin over the semiconductor substrate. The dielectric fin is between the first fin structure and the second fin structure. The dielectric fin has an inner portion and a protective layer. The protective layer extends along sidewalls and a bottom of the inner portion, and the protective layer has a dielectric constant higher than that of the inner portion.

Abstract: An embodiment includes a device including a first semiconductor fin extending from a substrate, a second semiconductor fin extending from the substrate, a hybrid fin over the substrate, the hybrid fin disposed between the first semiconductor fin and the second semiconductor fin, and the hybrid fin having an oxide inner portion extending downward from a top surface of the hybrid fin. The device also includes a first isolation region between the second semiconductor fin, the first semiconductor fin, and the hybrid fin, the hybrid fin extending above a top surface of the first isolation region, a high-k gate dielectric over sidewalls of the hybrid fin, sidewalls of the first semiconductor fin, and sidewalls of the second semiconductor fin, a gate electrode on the high-k gate dielectric, and source/drain regions on the first semiconductor fin on opposing sides of the gate electrode.

Abstract: A method of forming a semiconductor device including forming a fin structure having a stack of alternating first semiconductor layers and second semiconductor layers over a substrate, the first semiconductor layers and the second semiconductor layers having different compositions, forming a dummy gate structure across the fin structure, forming gate spacers on opposite sidewalls of the dummy gate structure, respectively, removing the dummy gate structure to form a gate trench between the gate spacers, etching the first semiconductor layers in the gate trench, such that the second semiconductor layers are suspended in the gate trench to serve as nanosheets, forming a work function metal layer surrounding each of the nanosheets, and depositing a fill metal layer over the work function metal layer without using a fluorine-containing precursor.

Abstract: In a method of manufacturing a semiconductor device, a fin structure is formed by patterning a semiconductor layer, an isolation insulating layer is formed such that an upper portion of the fin structure protrudes from the isolation insulating layer, a gate dielectric layer is formed by a deposition process, a nitridation operation is performed on the gate dielectric layer, and a gate electrode layer is formed over the gate dielectric layer. The gate dielectric layer as formed includes silicon oxide, and the nitridation operation comprises a plasma nitridation operation using a N2 gas and a NH3 gas.

Abstract: A method of forming a semiconductor device includes: forming a gate structure over a fin that protrudes above a substrate, the gate structure being surrounded by a first interlayer dielectric (ILD) layer; forming a trench in the first ILD layer adjacent to the fin; filling the trench with a first dummy material; forming a second ILD layer over the first ILD layer and the first dummy material; forming an opening in the first ILD layer and the second ILD layer, the opening exposing a sidewall of the first dummy material; lining sidewalls of the opening with a second dummy material; after the lining, forming a conductive material in the opening; after forming the conductive material, removing the first and the second dummy materials from the trench and the opening, respectively; and after the removing, sealing the opening and the trench by forming a dielectric layer over the second ILD layer.

Abstract: A method of forming a semiconductor device includes: forming a dummy gate structure over a nanostructure, where the nanostructure overlies a fin that protrudes above a substrate, where the nanostructure comprises alternating layers of a first semiconductor material and a second semiconductor material; forming openings in the nanostructure on opposing sides of the dummy gate structure, the openings exposing end portions of the first semiconductor material and end portions of the second semiconductor material; recessing the exposed end portions of the first semiconductor material to form first sidewall recesses; filling the first sidewall recesses with a multi-layer spacer film; removing at least one sublayer of the multi-layer spacer film to form second sidewall recesses; and forming source/drain regions in the openings after removing at least one sublayer, where the source/drain regions seal the second sidewall recesses to form sealed air gaps.

Abstract: A semiconductor structure according to the present disclosure includes a base fin over a substrate, a stack of nanostructures disposed directly over the base fin, a gate structure wrapping around each of the stack of nanostructures, an isolation feature disposed over the substrate and adjacent the base fin, and a dielectric fin disposed directly on the isolation feature. The dielectric includes in a bottom portion, a middle layer over the bottom portion and a top layer over the middle layer. The bottom portion includes an outer layer and an inner layer spaced apart from the gate structure and the isolation feature by the outer layer. The middle layer is in direct contact with top surfaces of the inner layer and the outer layer. The dielectric constant of the top layer of the dielectric fin is greater than the dielectric constant of the middle layer.

Abstract: A method includes depositing a first dielectric layer over and along sidewalls of a first semiconductor fin and a second semiconductor fin, where the first semiconductor fin and the second semiconductor fin extend upwards from a semiconductor substrate, depositing a second dielectric layer over the first dielectric layer, depositing a third dielectric layer over the second dielectric layer, where materials of the second dielectric layer and the third dielectric layer are different, and a material of the first dielectric layer is different from the material of the second dielectric layer and recessing the first dielectric layer and the second dielectric layer to expose sidewalls of the first semiconductor fin and the second semiconductor fin and to form a dummy fin between the first semiconductor fin and the second semiconductor fin.

Abstract: A semiconductor device structure and a formation method are provided. The method includes forming a fin structure over a substrate, and the fin structure has multiple sacrificial layers and multiple semiconductor layers laid out alternately. The method also includes removing the sacrificial layers to release multiple semiconductor nanostructures made up of remaining portions of the semiconductor lavers. The method further includes forming a gate dielectric layer to wrap around the semiconductor nanostructures and forming a first metal-containing layer over the gate dielectric layer to wrap around the semiconductor nanostructures. In addition, the method includes introducing oxygen-containing plasma on the first metal-containing layer to transform an upper portion of the first metal-containing layer into a metal oxide layer. The method includes forming a second metal-containing layer over the metal oxide layer.

Abstract: Semiconductor devices and methods of manufacture are presented in which spacers are manufactured on sidewalls of gates for semiconductor devices. In embodiments the spacers comprise a first seal, a second seal, and a contact etch stop layer, in which the first seal comprises a first shell along with a first bulk material, the second seal comprises a second shell along with a second bulk material, and the contact etch stop layer comprises a third bulk material and a second dielectric material.

Abstract: An embodiment is a semiconductor device including a first channel region over a semiconductor substrate, a second channel region over the first channel region, a first gate stack over the semiconductor substrate and surrounding the first channel region and the second channel region, a first inner spacer extending from the first channel region to the second channel region and along a sidewall of the first gate stack, a second inner spacer extending from the first channel region to the second channel region and along a sidewall of the first inner spacer, the second inner spacer having a different material composition than the first inner spacer, and a first source/drain region adjacent the first channel region, the second channel region, and the second inner spacer, the first and second inner spacers being between the first gate stack and the first source/drain region.

Abstract: Semiconductor devices including air gaps between source/drain regions and a semiconductor substrate and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a semiconductor substrate; a first channel region on the semiconductor substrate; a gate structure on the first channel region; a first source/drain region adjacent the gate structure and the first channel region; a first inner spacer layer between the first source/drain region and the semiconductor substrate in a first direction perpendicular to a major surface of the semiconductor substrate; and a first air gap between the first source/drain region and the first inner spacer layer in the first direction.

Abstract: In an embodiment, a device includes: a channel region; a gate dielectric layer on the channel region; a first work function tuning layer on the gate dielectric layer, the first work function tuning layer including a p-type work function metal; a barrier layer on the first work function tuning layer; a second work function tuning layer on the barrier layer, the second work function tuning layer including a n-type work function metal, the n-type work function metal different from the p-type work function metal; and a fill layer on the second work function tuning layer.

Abstract: A semiconductor device including a capacitor, with a memory film isolating a first electrode from a contact, formed over a transistor and methods of forming the same are disclosed. In an embodiment, a semiconductor device includes a gate stack over a semiconductor substrate; a capacitor over the gate stack, the capacitor including a first electrode extending along a top surface of the gate stack, the first electrode being U-shaped; a first ferroelectric layer over the first electrode; and a second electrode over the first ferroelectric layer, a top surface of the second electrode being level with a top surface of the first ferroelectric layer, and the top surface of the first ferroelectric layer and the top surface of the second electrode being disposed further from the semiconductor substrate than a topmost surface of the first electrode.

Abstract: A ferroelectric device structure includes an array of ferroelectric capacitors overlying a substrate, first metal interconnect structures electrically connecting each of first electrodes of the array of ferroelectric capacitors to a first metal pad embedded in a dielectric material layer, and second metal interconnect structures electrically connecting each of the second electrodes of the array of ferroelectric capacitors to a second metal pad embedded in the dielectric material layer. The second metal pad may be vertically spaced from the substrate by a same vertical separation distance as the first metal pad is from the substrate. First metal lines laterally extending along a first horizontal direction may electrically connect the first electrodes to the first metal pad, and second metal lines laterally extending along the first horizontal direction may electrically connect each of the second electrodes to the second metal pad.

Abstract: A method includes forming a semiconductor layer over a substrate; etching a portion of the semiconductor layer to form a first recess and a second recess; forming a first masking layer over the semiconductor layer; performing a first thermal treatment on the first masking layer, the first thermal treatment densifying the first masking layer; etching the first masking layer to expose the first recess; forming a first semiconductor material in the first recess; and removing the first masking layer.

Abstract: A test structure for 3D memory arrays and methods of forming the same are disclosed. In an embodiment, a memory array includes a first word line over a semiconductor substrate and extending in a first direction; a second word line over the first word line and extending in the first direction; a memory film contacting the first word line and the second word line; an oxide semiconductor (OS) layer contacting a first source line and a first bit line, the memory film being between the OS layer and each of the first word line and the second word line; and a test structure over the first word line and the second word line, the test structure including a first conductive line electrically coupling the first word line to the second word line, the first conductive line extending in the first direction.

Abstract: A semiconductor device and method of manufacture are provided. In embodiments a dielectric fin is formed in order to help isolate adjacent semiconductor fins. The dielectric fin is formed using a deposition process in which deposition times and temperatures are utilized to increase the resistance of the dielectric fin to subsequent etching processes.

Abstract: In an embodiment, a device includes: a first nanostructure; a second nanostructure; a gate dielectric around the first nanostructure and the second nanostructure, the gate dielectric including dielectric materials; and a gate electrode including: a work function tuning layer on the gate dielectric, the work function tuning layer including a pure work function metal, the pure work function metal of the work function tuning layer and the dielectric materials of the gate dielectric completely filling a region between the first nanostructure and the second nanostructure, the pure work function metal having a composition of greater than 95 at. % metals; an adhesion layer on the work function tuning layer; and a fill layer on the adhesion layer.