Abstract: A method, system and computer program for transmitting at least two payloads in a downstream traffic phase of a time-division duplex (TDD) cycle with a single preamble from a headend followed by concatenated payloads without intervening preambles, whereby the payloads are ranked by increasing modulation profiles. The preamble, and concatenated and ordered set of payloads are then transmitted to two or more predetermined customer premise equipments (CPEs).

Abstract: A method, system and computer program for transmitting at least two payloads in a downstream traffic phase of a time-division duplex (TDD) cycle with a single preamble from a headend followed by concatenated payloads without intervening preambles, whereby the payloads are ranked by increasing modulation profiles. The preamble, and concatenated and ordered set of payloads are then transmitted to two or more predetermined customer premise equipments (CPEs).

Abstract: A method, system and computer program for transmitting at least two payloads in a downstream traffic phase of a time-division duplex (TDD) cycle with a single preamble from a headend followed by concatenated payloads without intervening preambles, whereby the payloads are ranked by increasing modulation profiles. The preamble, and concatenated and ordered set of payloads are then transmitted to two or more predetermined customer premise equipments (CPEs).

Abstract: A method, system and computer program for transmitting at least two payloads in a downstream traffic phase of a time-division duplex (TDD) cycle with a single preamble from a headend followed by concatenated payloads without intervening preambles, whereby the payloads are ranked by increasing modulation profiles. The preamble, and concatenated and ordered set of payloads are then transmitted to two or more predetermined customer premise equipments (CPEs).

Abstract: A method, system and computer program for transmitting at least two payloads in a downstream traffic phase of a time-division duplex (TDD) cycle with a single preamble from a headend followed by concatenated payloads without intervening preambles, whereby the payloads are ranked by increasing modulation profiles. The preamble, and concatenated and ordered set of payloads are then transmitted to two or more predetermined customer premise equipments (CPEs).

Abstract: A method, system and computer program for transmitting at least two payloads in a downstream traffic phase of a time-division duplex (TDD) cycle with a single preamble from a headend followed by concatenated payloads without intervening preambles, whereby the payloads are ranked by increasing modulation profiles. The preamble, and concatenated and ordered set of payloads are then transmitted to two or more predetermined customer premise equipments (CPEs).

Abstract: A method, system and computer program for transmitting at least two payloads in a downstream traffic phase of a time-division duplex (TDD) cycle with a single preamble from a headend followed by concatenated payloads without intervening preambles, whereby the payloads are ranked by increasing modulation profiles. The preamble, and concatenated and ordered set of payloads are then transmitted to two or more predetermined customer premise equipments (CPEs).

Abstract: Systems and methods for provided for reducing interference caused by leakage of signals generated by a spread spectrum phase lock loop (SS PLL). Output of SS PLL may be processed to reduce interference. For example, a sinusoidal spreading signal may be used to spread the output of the SS PLL. A notch filter tracks the frequency of the output of the SS PLL to steer the notch in the filter to the instantaneous frequency output from the SS PLL, thus allowing the notch filter to be placed in the path of signals that have unwanted leakage from the SS PLL.

Abstract: A method, system and computer program for transmitting at least two payloads in a downstream traffic phase of a time-division duplex (TDD) cycle with a single preamble from a headend followed by concatenated payloads without intervening preambles, whereby the payloads are ranked by increasing modulation profiles. The preamble, and concatenated and ordered set of payloads are then transmitted to two or more predetermined customer premise equipments (CPEs).

Abstract: Systems and methods for generating a spurious signal cancellation signal, the system comprising two direct digital synthesizers (DDS). The first DDS provides phase tracking to correct for rounding errors. The second DDS outputs a frequency that is exactly equal to N/M*CLK, where N and M are values selected to set the output frequency equal to the frequency of a spurious signal to be cancelled, and CLK is a clock frequency used to clock the first and second DDS circuits.

Abstract: Systems and methods for generating a spurious signal cancellation signal, the system comprising two direct digital synthesizers (DDS). The first DDS provides phase tracking to correct for rounding errors. The second DDS outputs a frequency that is exactly equal to N/M*CLK, where N and M are values selected to set the output frequency equal to the frequency of a spurious signal to be cancelled, and CLK is a clock frequency used to clock the first and second DDS circuits.

Abstract: Systems and methods for provided for reducing interference caused by leakage of signals generated by a spread spectrum phase lock loop (SS PLL). Output of SS PLL may be processed to reduce interference. For example, a sinusoidal spreading signal may be used to spread the output of the SS PLL. A notch filter tracks the frequency of the output of the SS PLL to steer the notch in the filter to the instantaneous frequency output from the SS PLL, thus allowing the notch filter to be placed in the path of signals that have unwanted leakage from the SS PLL.

Abstract: Systems and methods for generating a spurious signal cancellation signal, the system comprising two direct digital synthesizers (DDS). The first DDS provides phase tracking to correct for rounding errors. The second DDS outputs a frequency that is exactly equal to N/M*CLK, where N and M are values selected to set the output frequency equal to the frequency of a spurious signal to be cancelled, and CLK is a clock frequency used to clock the first and second DDS circuits.

Abstract: Systems and methods for reducing interference caused by leakage of signals generated by a spread spectrum phase lock loop (SS PLL). The system and method uses a sinusoidal spreading signal to spread the output of a SS PLL. A notch filter tracks the frequency of the output of the SS PLL to steer the notch in the filter to the instantaneous frequency output from the SS PLL, thus allowing the notch filter to be placed in the path of signals that have unwanted leakage from the SS PLL.

Abstract: Systems and methods for generating a spurious signal cancellation signal, the system comprising two direct digital synthesizers (DDS). The first DDS provides phase tracking to correct for rounding errors. The second DDS outputs a frequency that is exactly equal to N/M*CLK, where N and M are values selected to set the output frequency equal to the frequency of a spurious signal to be cancelled, and CLK is a clock frequency used to clock the first and second DDS circuits.

Abstract: A method, system and computer program for transmitting at least two payloads in a downstream traffic phase of a time-division duplex (TDD) cycle with a single preamble from a headend followed by concatenated payloads without intervening preambles, whereby the payloads are ranked by increasing modulation profiles. The preamble, and concatenated and ordered set of payloads are then transmitted to two or more predetermined customer premise equipments (CPEs).

Abstract: Systems and methods for reducing interference caused by leakage of signals generated by a spread spectrum phase lock loop (SS PLL). The system and method uses a sinusoidal spreading signal to spread the output of a SS PLL. A notch filter tracks the frequency of the output of the SS PLL to steer the notch in the filter to the instantaneous frequency output from the SS PLL, thus allowing the notch filter to be placed in the path of signals that have unwanted leakage from the SS PLL.

Abstract: Systems and methods for generating a spurious signal cancellation signal, the system comprising two direct digital synthesizers (DDS). The first DDS provides phase tracking to correct for rounding errors. The second DDS outputs a frequency that is exactly equal to N/M*CLK, where N and M are values selected to set the output frequency equal to the frequency of a spurious signal to be cancelled, and CLK is a clock frequency used to clock the first and second DDS circuits.

Abstract: A satellite signal demodulator is configured to use frequency-based channel scanning to sense the presence of a channel and to obtain the frequency profile of the channel. Once the channel is identified and the profile is obtained, channel extraction is used to identify the frequency parameters for a given channel. A coarse parameter estimation is performed to obtain a coarse estimate of the symbol rate (SR) and the center frequency (fc) of the channel. The coarse estimation can then be followed by a fine estimation of the symbol rate and center frequency (fc), using a bit tracking loop (BTL) lock indicator.

Abstract: A modem for use with a computer having a demodulator and a decoder, the modem comprises a hardware interface; a demodulator front-end having a first input and a first output, the first output of the demodulator front-end being configured to interface with the demodulator of the computer and to provide a demodulated front-end signal to the demodulator over the hardware interface; and a forward error correction (FEC) unit having a second input and a second output, the second input of the FEC unit being configured to interface with the demodulator of the computer and to receive a demodulated signal from the demodulator over the hardware interface, the demodulated signal being a demodulation of the demodulated front-end signal, and the second output of the FEC unit being configured to interface with the decoder of the computer and to provide an FEC signal to the decoder over the hardware interface.