Abstract: A system for isolating individual channels in a broadcast signal is provided. The system includes a plurality of multipliers, each having an input and an output. A summer coupled to the outputs of each of the plurality of multipliers is provided to generate an output. A multiplication factor system provides a multiplication factor to each of the multipliers to select a predetermined frequency channel of the input signal.

Abstract: A satellite signal demodulator is configured to use frequency-based channel scanning to sense the presence of a channel and to obtain the frequency profile of the channel. Once the channel is identified and the profile is obtained, channel extraction is used to identify the frequency parameters for a given channel. A coarse parameter estimation is performed to obtain a coarse estimate of the symbol rate (SR) and the center frequency (fc) of the channel. The coarse estimation can then be followed by a fine estimation of the symbol rate and center frequency (fc), using a bit tracking loop (BTL) lock indicator.

Abstract: A system for signal processing is provided. The system includes a steady state processing system for receiving a signal. A general purpose processing system is coupled to the steady state processing system and includes a signal acquisition system for receiving the signal and generating acquisition data. The steady state processing system can receive the acquisition data from the signal acquisition system and use the acquisition data to acquire the signal.

Abstract: A satellite signal demodulator is configured to use frequency-based channel scanning to sense the presence of a channel and to obtain the frequency profile of the channel. Once the channel is identified and the profile is obtained, channel extraction is used to identify the frequency parameters for a given channel. A coarse parameter estimation is performed to obtain a coarse estimate of the symbol rate (SR) and the center frequency (fc) of the channel. The coarse estimation can then be followed by a fine estimation of the symbol rate and center frequency (fc), using a bit tracking loop (BTL) lock indicator.

Abstract: An erasures assisted block code decoder and related method are provided. The erasures assisted block code decoder includes a first block decoder, an erasures processor, and a second block code decoder. The first block decoder, for example, a Reed-Solomon decoder, is configured to decode blocks of data elements, e.g., bytes, that were previously affected by bursty errors. The first block decoder is also configured to identify those of such blocks it is unable to decode. The erasures processor is configured to identify, as erasures, data elements in the un-decodable blocks by utilizing, in the erasures identification process, data elements in the decoded blocks that were corrected by the first block decoder. The second block decoder, e.g., the same or different Reed-Solomon decoder, is configured to decode one or more of the un-decodable blocks by utilizing, in the decoding, the erasures identified by the erasures processor.

Abstract: A system for isolating individual channels in a broadcast signal is provided. The system includes a plurality of multipliers, each having an input and an output. A summer coupled to the outputs of each of the plurality of multipliers is provided to generate an output. A multiplication factor system provides a multiplication factor to each of the multipliers to select a predetermined frequency channel of the input signal.

Abstract: A system for isolating individual channels in a broadcast signal is provided. The system includes a plurality of multipliers, each having an input and an output. A summer coupled to the outputs of each of the plurality of multipliers is provided to generate an output. A multiplication factor system provides a multiplication factor to each of the multipliers to select a predetermined frequency channel of the input signal.

Abstract: A modem for use with a computer having a demodulator and a decoder, the modem comprises a hardware interface; a demodulator front-end having a first input and a first output, the first output of the demodulator front-end being configured to interface with the demodulator of the computer and to provide a demodulated front-end signal to the demodulator over the hardware interface; and a forward error correction (FEC) unit having a second input and a second output, the second input of the FEC unit being configured to interface with the demodulator of the computer and to receive a demodulated signal from the demodulator over the hardware interface, the demodulated signal being a demodulation of the demodulated front-end signal, and the second output of the FEC unit being configured to interface with the decoder of the computer and to provide an FEC signal to the decoder over the hardware interface.

Abstract: A modem for use with a computer having a demodulator and a decoder, the modem comprises a hardware interface; a demodulator front-end having a first input and a first output, the first output of the demodulator front-end being configured to interface with the demodulator of the computer and to provide a demodulated front-end signal to the demodulator over the hardware interface; and a forward error correction (FEC) unit having a second input and a second output, the second input of the FEC unit being configured to interface with the demodulator of the computer and to receive a demodulated signal from the demodulator over the hardware interface, the demodulated signal being a demodulation of the demodulated front-end signal, and the second output of the FEC unit being configured to interface with the decoder of the computer and to provide an FEC signal to the decoder over the hardware interface.

Abstract: An erasures assisted block code decoder and related method are provided. The erasures assisted block code decoder comprises a first block decoder, an erasures processor, and a second block code decoder. The first block decoder, for example, a Reed-Solomon decoder, is configured to decode blocks of data elements, e.g., bytes, that were previously affected by bursty errors. The first block decoder is also configured to identify those of such blocks it is unable to decode. The erasures processor is configured to identify, as erasures, data elements in the un-decodable blocks by utilizing, in the erasures identification process, data elements in the decoded blocks that were corrected by the first block decoder. The second block decoder, e.g., the same or different Reed-Solomon decoder, is configured to decode one or more of the un-decodable blocks by utilizing, in the decoding, the erasures identified by the erasures processor.

Abstract: An erasures assisted block code decoder and related method are provided. The erasures assisted block code decoder includes a first block decoder, an erasures processor, and a second block code decoder. The first block decoder, for example, a Reed-Solomon decoder, is configured to decode blocks of data elements, e.g., bytes, that were previously affected by bursty errors. The first block decoder is also configured to identify those of such blocks it is unable to decode. The erasures processor is configured to identify, as erasures, data elements in the un-decodable blocks by utilizing, in the erasures identification process, data elements in the decoded blocks that were corrected by the first block decoder. The second block decoder, e.g., the same or different Reed-Solomon decoder, is configured to decode one or more of the un-decodable blocks by utilizing, in the decoding, the erasures identified by the erasures processor.

Abstract: A system for signal processing is provided. A sampling delay system generates a plurality of sampling delay values. A plurality of programmable delays each receives one of the sample delay values. A plurality of sample and hold units, each coupled to one of the programmable delays, generates a sample of a received signal in response to an input from the programmable delay.

Abstract: A known sequence of symbols is located within a transmitted sequence of symbols by estimating the phase differences between offset symbols within a portion or more of the transmitted sequence, estimating the phase differences between offset symbols in the known sequence, and determining that the symbols within the portion or more of the transmitted sequence are the known sequence if the phase difference estimates determined from the symbols within the portion or more of the transmitted sequence are substantially equal to the phase difference estimates determined from the known sequence.

Abstract: A system for isolating individual channels in a broadcast signal is provided. The system includes a plurality of multipliers, each having an input and an output. A summer coupled to the outputs of each of the plurality of multipliers is provided to generate an output. A multiplication factor system provides a multiplication factor to each of the multipliers to select a predetermined frequency channel of the input signal.

Abstract: A satellite signal demodulator is configured to use frequency-based channel scanning to sense the presence of a channel and to obtain the frequency profile of the channel. Once the channel is identified and the profile is obtained, channel extraction is used to identify the frequency parameters for a given channel. A coarse parameter estimation is performed to obtain a coarse estimate of the symbol rate (SR) and the center frequency (fc) of the channel. The coarse estimation can then be followed by a fine estimation of the symbol rate and center frequency (fc), using a bit tracking loop (BTL) lock indicator.

Abstract: A system for signal processing is provided. A sampling delay system generates a plurality of sampling delay values. A plurality of programmable delays each receives one of the sample delay values. A plurality of sample and hold units, each coupled to one of the programmable delays, generates a sample of a received signal in response to an input from the programmable delay.

Abstract: A system for signal processing is provided. The system includes a steady state processing system for receiving a signal. A general purpose processing system is coupled to the steady state processing system and includes a signal acquisition system for receiving the signal and generating acquisition data. The steady state processing system can receive the acquisition data from the signal acquisition system and use the acquisition data to acquire the signal.

Abstract: A simultaneous multiple channel receiver (“SMCR”) for receiving a combined signal having a plurality of carrier signals, where each carrier signal in the plurality of carriers signals corresponds to a frequency channel, and in response, simultaneously producing a plurality of output data stream signals, is disclosed. The SMCR may include a down-converter front-end capable of receiving the combined signal, a plurality of digital signal processors, wherein each digital signal processor of the plurality of digital signal processors is capable of producing an output data stream signal of the plurality of output data stream signals, and a multi-band filter in signal communication with both the down-converter front-end and the plurality of digital signal processors.

Abstract: A modem for use with a computer having a demodulator and a decoder, the modem comprises a hardware interface; a demodulator front-end having a first input and a first output, the first output of the demodulator front-end being configured to interface with the demodulator of the computer and to provide a demodulated front-end signal to the demodulator over the hardware interface; and a forward error correction (FEC) unit having a second input and a second output, the second input of the FEC unit being configured to interface with the demodulator of the computer and to receive a demodulated signal from the demodulator over the hardware interface, the demodulated signal being a demodulation of the demodulated front-end signal, and the second output of the FEC unit being configured to interface with the decoder of the computer and to provide an FEC signal to the decoder over the hardware interface.

Abstract: Various embodiments of multipath processing systems and methods are disclosed. One method embodiment, among others, comprises the steps of providing a frequency domain channel response corresponding to a received signal, and applying a fast Fourier transform (FFT) on the frequency domain channel response to provide multi-path channel information.