Patents by Inventor Chi-Sheng Chen
Chi-Sheng Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145569Abstract: A semiconductor device includes a field effect transistor (FET). The FET includes a first channel, a first source and a first drain; a second channel, a second source and a second drain; and a gate structure disposed over the first and second channels. The gate structure includes a gate dielectric layer and a gate electrode layer. The first source includes a first crystal semiconductor layer and the second source includes a second crystal semiconductor layer. The first source and the second source are connected by an alloy layer made of one or more Group IV element and one or more transition metal elements. The first crystal semiconductor layer is not in direct contact with the second crystal semiconductor layer.Type: ApplicationFiled: January 4, 2024Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yee-Chia YEO, Sung-Li WANG, Chi On CHUI, Jyh-Cherng SHEU, Hung-Li CHIANG, I-Sheng CHEN
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Publication number: 20240136420Abstract: A thin film transistor includes a substrate, a semiconductor layer, a gate insulating layer, a gate, a source and a drain. The semiconductor layer is located above the substrate. The gate insulating layer is located above the semiconductor layer. The gate is located above the gate insulating layer and overlapping with the semiconductor layer. The gate includes a first portion, a second portion and a third portion. The first portion is extending along the surface of the gate insulating layer and directly in contact with the gate insulating layer. The second portion is separated from the gate insulating layer. Taking the surface of the gate insulating layer as a reference, the top surface of the second portion is higher than the top surface of the first portion. The third portion connects the first portion to the second portion. The source and the drain are electrically connected to the semiconductor layer.Type: ApplicationFiled: December 1, 2022Publication date: April 25, 2024Applicant: AUO CorporationInventors: Kuo-Jui Chang, Wen-Tai Chen, Chi-Sheng Chiang, Yu-Chuan Liao, Chien-Sen Weng, Ming-Wei Sun
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Publication number: 20240136481Abstract: A micro light-emitting diode display device includes a substrate, a first planarization layer, a first light-emitting element, and a second planarization layer. The first planarization layer is disposed on the substrate and has a first opening. The first opening has a first opening inner wall. The first light-emitting element is disposed on the substrate, in the first opening, and separated from the first opening inner wall. The second planarization layer is disposed on the substrate and between the first planarization layer and the first light-emitting element. The second planarization layer is in contact with the first light-emitting element.Type: ApplicationFiled: October 18, 2023Publication date: April 25, 2024Inventors: Bin-Cheng LIN, Chieh-Ming Chen, Bo-Ru Jian, Chi-Sheng Liao, Ta-Wen Liao
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Publication number: 20240127783Abstract: Provided are a noise cancellation method and apparatus, an electronic device, a noise cancellation earphone, and a storage medium. The method includes acquiring original sound source information; performing noise reduction (NR) processing on the original sound source information using active noise cancellation (ANC) to obtain first sound information and performing the NR processing on the original sound source information using environmental noise cancellation (ENC) to obtain second sound information; and mixing and adding the first sound information and the second sound information to obtain target sound information and playing the target sound information. In this method, the NR processing can be performed on the sound using the ANC and the ENC, thereby distinguishing environmental noise from human voice, improving the noise cancellation performance, and enabling a user to hear clearer sound.Type: ApplicationFiled: April 3, 2023Publication date: April 18, 2024Applicant: Lanto Electronic LimitedInventors: Che-Yung Huang, Chi-Liang Chen, Yong-Sheng Jheng, Che-Yi HSIAO
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Publication number: 20240128626Abstract: A transmission device includes a daisy chain structure composed of at least three daisy chain units arranged periodically and continuously. Each of the daisy chain units includes first, second and third conductive lines, and first and second conductive pillars. The first and second conductive lines at a first layer extend along a first direction and are discontinuously arranged. The third conductive line at a second layer extends along the first direction and is substantially parallel to the first and second conductive lines. The first conductive pillar extends in a second direction. The second direction is different from the first direction. A first part of the first conductive pillar is connected to the first and third conductive lines. The second conductive pillar extends in the second direction. A first part of the second conductive pillar is connected to the second and third conductive lines.Type: ApplicationFiled: November 25, 2022Publication date: April 18, 2024Applicants: UNIMICRON TECHNOLOGY CORP., National Taiwan UniversityInventors: Yu-Kuang WANG, Ruey-Beei Wu, Ching-Sheng Chen, Chun-Jui Huang, Wei-Yu Liao, Chi-Min Chang
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Publication number: 20240130038Abstract: A transmission device for suppressing the glass-fiber effect includes a circuit board and a transmission line. The circuit board includes a plurality of glass fibers, so as to define a fiber pitch. The transmission line is disposed on the circuit board. The transmission line includes a plurality of non-parallel segments. Each of the non-parallel segments of the transmission line has an offset distance with respect to a reference line. The offset distance is longer than or equal to a half of the fiber pitch.Type: ApplicationFiled: November 23, 2022Publication date: April 18, 2024Applicants: UNIMICRON TECHNOLOGY CORP., National Taiwan UniversityInventors: Chin-Hsun WANG, Ruey-Beei Wu, Ching-Sheng Chen, Chun-Jui Hung, Wei-Yu Liao, Chi-Min Chang
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Patent number: 11940737Abstract: A method includes receiving a device design layout and a scribe line design layout surrounding the device design layout. The device design layout and the scribe line design layout are rotated in different directions. An optical proximity correction (OPC) process is performed on the rotated device design layout and the rotated scribe line design layout. A reticle includes the device design layout and the scribe line design layout is formed after performing the OPC process.Type: GrantFiled: May 7, 2021Date of Patent: March 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hsueh-Yi Chung, Yung-Cheng Chen, Fei-Gwo Tsai, Chi-Hung Liao, Shih-Chi Fu, Wei-Ti Hsu, Jui-Ping Chuang, Tzong-Sheng Chang, Kuei-Shun Chen, Meng-Wei Chen
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Patent number: 11921001Abstract: A method and system for inspecting deviation in dynamic characteristics of a feeding system are provided, and the method includes: exciting the feeding system and detecting vibrations of a subcomponent of a component to be inspected of the feeding system to generate a monitoring excitation signal in a monitoring mode; calculating, by a modal analysis method, monitoring eigenvalues and monitoring eigenvectors of the monitoring excitation signal; determining, by a modal verification method, similarity between the monitoring eigenvalues and standard eigenvalues of a digital twin model and similarity between the monitoring eigenvectors and standard eigenvectors of the digital twin model; determining that the dynamic characteristics of the subcomponent are deviated, when the monitoring eigenvalues and monitoring eigenvectors are not similar to the standard eigenvalues and standard eigenvectors. Therefore, the subcomponent whose dynamic characteristics are deviated can be sensed remotely and precisely.Type: GrantFiled: March 11, 2022Date of Patent: March 5, 2024Assignee: Hiwin Technologies Corp.Inventors: Hsien-Yu Chen, Yu-Sheng Chiu, Chih-Chun Cheng, Wen-Nan Cheng, Chi-Ming Liu
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Patent number: 11923252Abstract: A semiconductor device includes a first set of nanostructures stacked over a substrate in a vertical direction, and each of the first set of nanostructures includes a first end portion and a second end portion, and a first middle portion laterally between the first end portion and the second end portion. The first end portion and the second end portion are thicker than the first middle portion. The semiconductor device also includes a first plurality of semiconductor capping layers around the first middle portions of the first set of nanostructures, and a gate structure around the first plurality of semiconductor capping layers.Type: GrantFiled: January 27, 2021Date of Patent: March 5, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Sai-Hooi Yeong, Bo-Feng Young, Chi-On Chui, Chih-Chieh Yeh, Cheng-Hsien Wu, Chih-Sheng Chang, Tzu-Chiang Chen, I-Sheng Chen
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POLYIMIDE POLYMER, AND POLYIMIDE FILM INCLUDING THE SAME, AND MANUFACTURING METHOD OF POLYIMIDE FILM
Publication number: 20200165391Abstract: A polyimide polymer includes a first monomeric unit from dianhydride and a second monomeric unit from diamine, and the dianhydride includes 1,4-bis(3,4-dicarboxyphenoxy)benzene dianhydride (HQDPA), and coefficient of thermal expansion (CTE) is below 60 ppm/° C. The polyimide film includes a film layer, and the film layer includes the above polyimide polymer. The film layer optionally includes a pigment and an inorganic nanoparticle. Therefore, the thermal resistance and the transparency of the polyimide film are improved, and the polyimide film having high thermal resistances with different colors is available.Type: ApplicationFiled: December 12, 2018Publication date: May 28, 2020Applicant: MORTECH CORPORATIONInventors: Der-Jen SUN, Chi Sheng CHEN, Chang Lin LU -
Publication number: 20190023576Abstract: A method of manufacturing composite material containing artificial graphite is disclosed. An artificial graphite powder and a first solvent are mixed together to obtain a graphite dispersion solution, and a particle size of the graphite powder is less than 50 ?m. The graphite dispersion solution and a polyamic acid solution are mixed together to obtain a liquid mixture. The liquid mixture is heated to obtain a polyamic acid film containing artificial graphite powder. The imidization of the polyamic acid film is performed to obtain the composite material containing artificial graphite. A method of manufacturing a graphite sheet by using the composite material containing artificial graphite as raw material is disclosed.Type: ApplicationFiled: July 19, 2018Publication date: January 24, 2019Applicant: MORTECH CORPORATIONInventors: Der-Jen SUN, Chi-Sheng CHEN, Yen-Huey HSU
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Patent number: 9499664Abstract: A polyimide polymer, polyimide film and polyimide laminate plate including the same are provided. The polyimide polymer includes Formula (I), Formula (II) and Formula (III). In Formula (I), Formula (II) and Formula (III), A is an aromatic group with fluorine, B, B?, and B? are aromatic groups different from one another. B/(B+B?+B?), B?/(B+B?+B?), and B?/(B+B?+B?) are larger than 0. The polyimide film includes a film layer which includes the above polyimide polymer. The film layer optionally includes colorants or inorganic nanoparticles. Therefore, the thermal resistance and the transparency of the polyimide film are improved, and a polyimide film with high thermal resistance and different colors is available. The polyimide solution can also be applied on metal film to form polyimide laminate plate.Type: GrantFiled: February 5, 2015Date of Patent: November 22, 2016Assignee: MORTECH CORPORATIONInventors: Der-Jen Sun, Chi-Sheng Chen, Kuo-Wei Li, Yen-Huey Hsu
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Publication number: 20160122483Abstract: A polyimide polymer, polyimide film and polyimide laminate plate including the same are provided. The polyimide polymer includes Formula (I), Formula (II) and Formula (III). In Formula (I), Formula (II) and Formula (III), A is an aromatic group with fluorine, B, B?, and B? are aromatic groups different from one another. B/(B+B?+B?), B?/(B+B?+B?), and B?/(B+B?+B?) are larger than 0. The polyimide film includes a film layer which includes the above polyimide polymer. The film layer optionally includes colorants or inorganic nanoparticles. Therefore, the thermal resistance and the transparency of the polyimide film are improved, and a polyimide film with high thermal resistance and different colors is available. The polyimide solution can also be applied on metal film to form polyimide laminate plate.Type: ApplicationFiled: February 5, 2015Publication date: May 5, 2016Inventors: Der-Jen SUN, Chi-Sheng CHEN, Kuo-Wei LI, Yen-Huey HSU
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Patent number: 9075574Abstract: A touch panel includes a substrate, a touch device, a white translucent pattern, a color filter pattern and a reflection pattern. The substrate has a transparent region and an opaque region surrounding the transparent region. The touch device is disposed on the substrate in the transparent region. The white translucent pattern is disposed on the substrate in the opaque region. The color filter pattern stacks on the white translucent pattern in the opaque region. The reflection pattern stacks on the color filter pattern in the opaque region.Type: GrantFiled: July 5, 2013Date of Patent: July 7, 2015Assignee: AU Optronics Corp.Inventors: Chia-Chien Peng, Chi-Sheng Chen
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Patent number: 8883033Abstract: A method for removing silicon nitride material includes following steps. A substrate having at least a gate structure formed thereon is provided, and at least a silicon nitride hard mask is formed on top of the gate structure. A first removal is performed to remove a portion of the silicon nitride hard mask with a first phosphoric acid (H3PO4) solution. A second removal is subsequently performed to remove remnant silicon nitride hard mask with a second phosphoric acid solution. The first removal and the second removal are performed in-situ. A temperature of the second phosphoric acid solution is lower than a temperature of the first phosphoric acid solution.Type: GrantFiled: March 5, 2013Date of Patent: November 11, 2014Assignee: United Microelectronics Corp.Inventors: Chi-Sheng Chen, Shin-Chi Chen, Chih-Yueh Li, Ted Ming-Lang Guo, Bo-Syuan Lee, Tsung-Hsun Tsai, Yu-Chin Cheng
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Publication number: 20140256151Abstract: A method for removing silicon nitride material includes following steps. A substrate having at least a gate structure formed thereon is provided, and at least a silicon nitride hard mask is formed on top of the gate structure. A first removal is performed to remove a portion of the silicon nitride hard mask with a first phosphoric acid (H3PO4) solution. A second removal is subsequently performed to remove remnant silicon nitride hard mask with a second phosphoric acid solution. The first removal and the second removal are performed in-situ. A temperature of the second phosphoric acid solution is lower than a temperature of the first phosphoric acid solution.Type: ApplicationFiled: March 5, 2013Publication date: September 11, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chi-Sheng Chen, Shin-Chi Chen, Chih-Yueh Li, Ted Ming-Lang Guo, Bo-Syuan Lee, Tsung-Hsun Tsai, Yu-Chin Cheng
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Publication number: 20140160366Abstract: A touch panel includes a substrate, a touch device, a white translucent pattern, a color filter pattern and a reflection pattern. The substrate has a transparent region and an opaque region surrounding the transparent region. The touch device is disposed on the substrate in the transparent region. The white translucent pattern is disposed on the substrate in the opaque region. The color filter pattern stacks on the white translucent pattern in the opaque region. The reflection pattern stacks on the color filter pattern in the opaque region.Type: ApplicationFiled: July 5, 2013Publication date: June 12, 2014Inventors: Chia-Chien Peng, Chi-Sheng Chen
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Publication number: 20130134565Abstract: A method of fabricating a system-in-package (SiP) module is provided, which includes: providing a substrate having a plurality of scribe lines formed thereon, forming ground pads and ground vias along the scribe lines, disposing at least one electronic component on the substrate, forming on the substrate an encapsulant for encapsulating the electronic component, cutting the substrate along the scribe lines so as to expose the ground vias, and forming a shielding layer on the encapsulant and the ground vias to thereby obtain a plurality of SiP modules. Therefore, electromagnetic radiation interferences are avoided and the design complexity and fabrication cost are reduced.Type: ApplicationFiled: February 7, 2012Publication date: May 30, 2013Applicants: ASKEY COMPUTER CORPORATION, ASKEY TECHNOLOGY (JIANGSU) LTD.Inventors: Chi-Sheng Chen, Ching-Feng Hsieh
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Publication number: 20130133940Abstract: A system in package module and a method of fabricating the system in package module are disclosed. A substrate is provided, including circuit layers, solder pads and dielectric layers. Cutting lines are formed on the substrate. Grounded buried vias are formed in at least one dielectric layer and the circuit layers adjacent to the dielectric layer corresponding to the cutting lines. Electronic elements are disposed on the substrate. An encapsulant is formed on the substrate to encapsulate the electronic elements. The substrate is cut along the cutting lines to expose the grounded buried via. A shielding layer is formed enclosing the encapsulant and sidewalls of the substrate to obtain the system in package module. Therefore, the interference of electromagnetic radiation is diminished and less spaces on the top and bottom of the substrate are occupied.Type: ApplicationFiled: January 5, 2012Publication date: May 30, 2013Applicants: ASKEY COMPUTER CORPORATION, ASKEY TECHNOLOGY (JIANGSU) LTD.Inventors: Chi-Sheng Chen, Ching-Feng Hsieh
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Publication number: 20100271785Abstract: A heat-dissipating and fixing mechanism of an electronic component includes a heat-dissipating element, a circuit board and a thermally-conductive adhesive interface. The circuit board has multiple insertion holes. The pins of the electronic component are inserted into corresponding insertion holes of the circuit board. The thermally-conductive adhesive interface has a first surface bonded with the heat-dissipating element and a second surface bonded with the electronic component. As a consequence, the electronic component is fixed on the heat-dissipating element through the thermally-conductive adhesive interface, and the heat generated by the electronic component is transmitted to the heat-dissipating element through the thermally-conductive adhesive interface.Type: ApplicationFiled: June 22, 2009Publication date: October 28, 2010Inventors: Hung-Chang Hsieh, Chi-Sheng Chen, Ren-Shen Huang