Abstract: A system includes a first nonvolatile memory array, a second nonvolatile memory array, and a memory controller. The memory controller is configured to write an indicator bit to the second nonvolatile memory array, determine whether the indicator bit is valid in response to a power up of the system after a high-temperature event, a received command after a high-temperature event, a predetermined number of power ups, or a power up or received command after each of a predetermined number of high-temperature events, and write data stored in the second nonvolatile memory array to the first nonvolatile memory array when the indicator bit is valid.

Abstract: The invention provides a resistive memory apparatus including at least one first resistive memory cell, a first bit line selecting switch, a first source line selecting switch, a first pull down switch and a second pull down switch. The first bit line selecting switch is coupled between a first bit line and a sense amplifier. The first source line selecting switch is coupled between a source line and the sense amplifier. The first and second pull down switches are respectively coupled to the bit line and source line. When a reading operation is operated, on or off statuses of the first bit line selecting switch and the second pull down switch are the same, on or off statuses of the first source line selecting switch and the first pull down switch are the same, and on or off statuses of the first and second pull down switches are complementary.

Abstract: A system includes a first nonvolatile memory array, a second nonvolatile memory array, and a memory controller. The memory controller is configured to write an indicator bit to the second nonvolatile memory array, determine whether the indicator bit is valid in response to a power up of the system after a high-temperature event, a received command after a high-temperature event, a predetermined number of power ups, or a power up or received command after each of a predetermined number of high-temperature events, and write data stored in the second nonvolatile memory array to the first nonvolatile memory array when the indicator bit is valid.

Abstract: A memory system includes a resistive nonvolatile memory array configured to store data and error correction code (ECC) bits and a memory controller. The memory controller is configured to detect a number of errors among the stored look-ahead bits, compare the number of look-ahead bit errors to a threshold number of bit errors, perform a strong refresh of the data and look-ahead bits stored in the resistive nonvolatile memory array when the number of look-ahead bit errors equals or exceeds the threshold, and perform a weak refresh of the data and look-ahead bits by refreshing only units of stored data having data bit errors and look-ahead bits having look-ahead bit errors when the number of look-ahead bit errors is less than the threshold.

Abstract: A system includes a first nonvolatile memory array, a second nonvolatile memory array, and a memory controller. The memory controller is configured to write an indicator bit to the second nonvolatile memory array, determine whether the indicator bit is valid in response to a power up of the system after a high-temperature event, a received command after a high-temperature event, a predetermined number of power ups, or a power up or received command after each of a predetermined number of high-temperature events, and write data stored in the second nonvolatile memory array to the first nonvolatile memory array when the indicator bit is valid.

Abstract: The present invention discloses a reference cell circuit which is applied to a non-volatile memory. The reference cell circuit includes a reference cell array, a first current mirror circuit, and a second current mirror circuit. The reference cell array includes at least one row of floating gate transistors. The first current mirror circuit is arranged to generate a mirror current according to a reference current generated by the reference cell array. The second current mirror circuit is arranged to receive the mirror current and generate an adjusted reference current according to the mirror current and a selected one of a plurality of enable signals, wherein the plurality of enable signals correspond to a plurality operations of the non-volatile memory and the adjusted reference current is arranged to determine logical state of a plurality of memory cells of the non-volatile memory.

Abstract: The present invention discloses a reference cell circuit which is applied to a non-volatile memory. The reference cell circuit includes a reference cell array, a first current mirror circuit, and a second current mirror circuit. The reference cell array includes at least one row of floating gate transistors. The first current mirror circuit is arranged to generate a mirror current according to a reference current generated by the reference cell array. The second current mirror circuit is arranged to receive the mirror current and generate an adjusted reference current according to the mirror current and a selected one of a plurality of enable signals, wherein the plurality of enable signals correspond to a plurality operations of the non-volatile memory and the adjusted reference current is arranged to determine logical state of a plurality of memory cells of the non-volatile memory.