Abstract: The present invention provides a receiver including an ADC, an echo-cancellation circuit and a control circuit. In the operations of the receiver, the ADC uses a clock signal to perform an analog-to-digital converting operation on an analog input signal to generate digital input signal, the echo-cancellation circuit refers to a plurality of tap coefficients to perform an echo-cancellation operation on the digital input signal to generate an output signal, and the control circuit is configured to control a phase of the clock signal inputted into the ADC. In addition, when the phase of the clock signal is adjusted, the control circuit calculates a plurality of updated tap coefficients according to the plurality of tap coefficients used by the echo-cancellation circuit in a previous time, for use of the echo-cancellation circuit.

Abstract: The present invention provides a receiver including an ADC, an echo-cancellation circuit and a control circuit. In the operations of the receiver, the ADC uses a clock signal to perform an analog-to-digital converting operation on an analog input signal to generate digital input signal, the echo-cancellation circuit refers to a plurality of tap coefficients to perform an echo-cancellation operation on the digital input signal to generate an output signal, and the control circuit is configured to control a phase of the clock signal inputted into the ADC. In addition, when the phase of the clock signal is adjusted, the control circuit calculates a plurality of updated tap coefficients according to the plurality of tap coefficients used by the echo-cancellation circuit in a previous time, for use of the echo-cancellation circuit.

Abstract: An integrated circuit includes a Built-In Self-Test (BIST) circuit, a predetermined signature pattern and a Read Only Memory (ROM), wherein the predetermined signature pattern is stored in the integrated circuit. The ROM stores at least effective information and a BIST signature adjustment code, the BIST signature adjustment code is irrelevant to any functional information stored in the ROM; wherein the BIST circuit is used to test content stored in the ROM to generate a signature pattern, and compare the signature pattern with the predetermined signature pattern to judge if the content stored in the ROM has error.

Abstract: A method applied to a wired network including a first network device and a second network device is disclosed. The first and second network devices each include a first set of connection ends and a second set of connection ends. Firstly, the first network device transmits a specific signal pattern through its first set and second set of connection ends. Then, the first network device detects whether a signal is received at its first set and second set of connection ends. If it is determined that a signal is not received at the first set connection ends while a signal is received at the second set connection ends, the first network device determines that its second set of connection ends is not correctly coupled to the second set of connection ends of the second network device.

Abstract: This disclosure provides an apparatus for generating a spread-spectrum clock, which comprises: a multi-phase clock generator generating a pre-determined number of first clock signals having substantially identical period and different phases; a spread spectrum clock controller producing an instruction signal according to a first pre-determined spread spectrum target; and a clock selector receiving the instruction signal and dynamically selecting a clock signal from the first clock signals according to the instruction signal so as to produce a first spread spectrum signal; wherein the first spread spectrum signal has a spread spectrum corresponding to the first pre-determined spread spectrum target.

Abstract: A digital circuit design method includes: before performing physical design: performing a logic synthesis according to a Register Transfer Level (RTL) design and a plurality of constraints to at least generate a netlist, a standard delay format file and a first constraint file; retrieving information of at least a specific node of circuit from the first constraint file to generate a second constraint file; generating an updated standard delay format file at least according to the standard delay format file and the second constraint file, wherein a delay of the specific node of the updated standard delay format file is less than a delay of the specific node of the standard delay format file; and using the netlist and the updated standard delay format file to perform a pre-post-layout simulation.

Abstract: An integrated circuit is disclosed, including at least one configuration pin, an interface circuit, a detecting circuit, a determining circuit and a storage unit. A physical layer circuit of the invention not only increases the flexibility of setting PHY addresses, but also reduces the number of configuration pins.

Abstract: This disclosure provides an apparatus for generating a spread-spectrum clock, which comprises: a multi-phase clock generator generating a pre-determined number of first clock signals having substantially identical period and different phases; a spread spectrum clock controller producing an instruction signal according to a first pre-determined spread spectrum target; and a clock selector receiving the instruction signal and dynamically selecting a clock signal from the first clock signals according to the instruction signal so as to produce a first spread spectrum signal; wherein the first spread spectrum signal has a spread spectrum corresponding to the first pre-determined spread spectrum target.

Abstract: A digital circuit design method includes: before performing physical design: performing a logic synthesis according to a Register Transfer Level (RTL) design and a plurality of constraints to at least generate a netlist, a standard delay format file and a first constraint file; retrieving information of at least a specific node of circuit from the first constraint file to generate a second constraint file; generating an updated standard delay format file at least according to the standard delay format file and the second constraint file, wherein a delay of the specific node of the updated standard delay format file is less than a delay of the specific node of the standard delay format file; and using the netlist and the updated standard delay format file to perform a pre-post-layout simulation.

Abstract: An integrated circuit includes a Built-In Self-Test (BIST) circuit, a predetermined signature pattern and a Read Only Memory (ROM), wherein the predetermined signature pattern is stored in the integrated circuit. The ROM stores at least effective information and a BIST signature adjustment code, the BIST signature adjustment code is irrelevant to any functional information stored in the ROM; wherein the BIST circuit is used to test content stored in the ROM to generate a signature pattern, and compare the signature pattern with the predetermined signature pattern to judge if the content stored in the ROM has error.

Abstract: A controlling circuit supporting a power saving mechanism includes: a transmitting interface arranged to perform a signal transmission with a specific controlling circuit; and a setting unit coupled to the transmitting interface. The setting unit is arranged to control the specific controlling circuit to operate in the power saving mechanism.

Abstract: A method applied to a wired network including a first network device and a second network device is disclosed. The first and second network devices each include a first set of connection ends and a second set of connection ends. Firstly, the first network device transmits a specific signal pattern through its first set and second set of connection ends. Then, the first network device detects whether a signal is received at its first set and second set of connection ends. If it is determined that a signal is not received at the first set connection ends while a signal is received at the second set connection ends, the first network device determines that its second set of connection ends is not correctly coupled to the second set of connection ends of the second network device.

Abstract: The present invention discloses a circuit lifetime measuring device to estimate the rest lifetime of a target circuit, comprising: a reference clock receiving end for receiving a reference clock; a correlation signal generating circuit for providing a correlation signal in which at least some operating settings of the correlation signal generating circuit and the target circuit vary synchronously; a storage circuit for storing an initial relation between the reference clock and the correlation signal; a measuring circuit, coupled to the reference clock receiving end and the correlation signal generating circuit, for measuring a present relation between the reference clock and the correlation signal; and an estimating circuit, coupled to the storage circuit and the measuring circuit, for generating an estimation value according to the initial relation and the present relation, wherein the estimation value indicates the rest lifetime of the target circuit.

Abstract: A method applied to a wired network including a first network device and a second network device is disclosed. The first and second network devices each include a first set of connection ends and a second set of connection ends. Firstly, the first network device transmits a specific signal pattern through its first set and second set of connection ends. Then, the first network device detects whether a signal is received at its first set and second set of connection ends. If it is determined that a signal is not received at the first set connection ends while a signal is received at the second set connection ends, the first network device determines that its second set of connection ends is not correctly coupled to the second set of connection ends of the second network device.

Abstract: An apparatus and method for cross clock domain interference cancellation is provided to a communication system which includes a transmitter operated in a first clock domain and a receiver operated in a second clock domain. The apparatus comprises a First-In-First-Out (FIFO) circuit and a cancellation signal generator. The FIFO circuit receives a digital transmission signal of the transmitter in the first clock domain, and outputs the digital transmission signal in the second clock domain according to an accumulated timing difference between the first and second clock domains. The cancellation signal generator generates a cancellation signal for canceling an interference signal received by the receiver according to the digital transmission signal outputted by the FIFO circuit. The interference signal is generated in response to the digital transmission signal.

Abstract: A master/slave decision device applied to a first network device is provided, where the first network device is coupled to a second network device, and the master/slave decision device includes a seed distance detection unit and a decision unit. The seed distance decision unit is utilized for detecting a seed distance between a first seed utilized in a first scrambler of the first network device and a second seed utilized in a second scrambler of the second network device. The decision unit is coupled to the seed distance detecting unit, and is utilized for determining the first network device to be a master device or a slave device according to the seed distance.

Abstract: A power consumption control method applied to a communication system adjusts the power consumption of a portion of circuit in the communication system according to a transmission distance between the communication system and another communication system. Another power consumption control method applied to a communication system adjusts the power consumption of a portion of circuit in the communication system according to a signal index of the communication system.

Abstract: The present invention provides an configuration setting device of integrated circuit and the configuration setting method thereof, in which the configuration setting device comprises a signal receiving terminal, a voltage output unit coupled to the signal receiving terminal, and a detector coupled to the signal receiving terminal. The signal receiving terminal is used to receive the input signal at the outer of the integrated circuit, and the voltage output unit generated at the inner of the integrated circuit is used to output a voltage signal based on the enable signal, and the detector is used to detect a level at the signal receiving terminal to output a configuration signal; wherein, the signal level generated at the signal receiving terminal is determined by the input signal and the voltage signal.

Abstract: A device for allocating a number of taps of a designated finite impulse response filter is disclosed. The device comprises a plurality of designated finite impulse response filters having fixed number of taps, a plurality of allocation finite impulse response filters having fixed number of taps, a control unit and an estimate unit. Depending on intensities of responses to interferences, at least one of the allocation FIR filters may be coupled in series to any one of the designated finite impulse response filters, thereby to provide a signal having excellent quality.

Abstract: An apparatus and method for cross clock domain interference cancellation is provided to a communication system which includes a transmitter operated in a first clock domain and a receiver operated in a second clock domain. The apparatus comprises a First-In-First-Out (FIFO) circuit and a cancellation signal generator. The FIFO circuit receives a digital transmission signal of the transmitter in the first clock domain, and outputs the digital transmission signal in the second clock domain according to an accumulated timing difference between the first and second clock domains. The cancellation signal generator generates a cancellation signal for canceling an interference signal received by the receiver according to the digital transmission signal outputted by the FIFO circuit. The interference signal is generated in response to the digital transmission signal.