Abstract: A hierarchical representation encapsulates the detailed internal composition of a sub-circuit using the notion of a cell definition (a CellDef). The CellDef serves as a natural unit for operational reuse. If the computation required for the analysis or manipulation (e.g. parasitic extraction, RET, design rule confirmation (DRC), or OPC) based on a CellDef or one cell instance can be applied, with no or minimal additional effort, to all or a significant subset of other instances of the cell, very substantial reduction in computational effort may be realized. Furthermore, a hierarchical representation also allows for the partitioning of the overall analysis/manipulation task into a collection of subtasks, e.g. one per CellDef. Multiple jobs may then be distributed across a large number of computational nodes on a network for concurrent execution. While this may not reduce the aggregate computational time, a major reduction in the overall turnaround time (TAT) is in itself extremely beneficial.

Abstract: The present invention provides a system and method of modifying the mask layout shapes of an integrated circuit layout design to compensate for reticle field location-specific systematic CD variations resulting from mask writing process variations, lens imperfections in lithographic patterning, and photoresist process variations. Called PLC (Process-optimized Layout Compensation), each set of compensation rules according to the present invention is specifically tailored for a particular mask-writer-patterning-tools-and-resist-process combination, and are performed on a reticle-wide basis. Furthermore, for each geometric shape in the mask layout, the amount of modification is determined based on a categorization of the type of the shape, the specific location in the reticle field the particular shape falls in, its context (i.e., surrounding patterns, orientation, etc.), as well as certain photoresist parameters to be used in the patterning process.

Abstract: A method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips. More particularly, a method for generating an OPC model is provided which takes into consideration across-wafer variations which occur during the process of manufacturing semiconductor chips based on the parameters of test patterns measured at the “wafer sweet spots” so as to arrive at an accurate model.

Abstract: An apparatus and method of synthesizing a photolithographic data set includes using a first computational model to calculate a first figure-of-merit for the photolithographic data set; changing a first part of the photolithographic data set to increase the first figure-of-merit; and then using a second computational model to calculate a second figure-of-merit of the photolithographic data set; and changing a second part of the photolithographic data set to increase the second figure-of-merit. The second computational model enables figure-of-merit calculations to be executed at a significantly faster execution rate that the first computational model.

Abstract: A hierarchical representation encapsulates the detailed internal composition of a sub-circuit using the notion of a cell definition (a CellDef). The CellDef serves as a natural unit for operational reuse. If the computation required for the analysis or manipulation (e.g. parasitic extraction, RET, design rule confirmation (DRC), or OPC) based on a CellDef or one cell instance can be applied, with no or minimal additional effort, to all or a significant subset of other instances of the cell, very substantial reduction in computational effort may be realized. Furthermore, a hierarchical representation also allows for the partitioning of the overall analysis/manipulation task into a collection of subtasks, e.g. one per CellDef. Multiple jobs may then be distributed across a large number of computational nodes on a network for concurrent execution. While this may not reduce the aggregate computational time, a major reduction in the overall turnaround time (TAT) is in itself extremely beneficial.

Abstract: A cooling/heating system is disclosed which includes a compressor, an indoor heat exchanger, an expansion device, and an outdoor heat exchanger which are connected in series via a refrigerant line, wherein a refrigerant, which flows through the refrigerant line, heat-exchanges with supply water. A method for controlling the cooling/heating system is also disclosed.

Abstract: The present invention relates to air conditioning systems, and more particularly, to an air conditioning system which can control a refrigerant flow rate to a heat exchanger exchanging heat with room air to be optimum; and a method for controlling the same. The air conditioning system includes an outdoor heat exchange part including a compressor for compressing refrigerant, an outdoor heat exchanger for making the refrigerant to heat exchange with outdoor air, and an expansion device for expanding the refrigerant, an indoor heat exchange part including a pump for making refrigerant in a flow path independent from the outdoor heat exchange part to flow, at least one indoor heat exchanger for making the refrigerant heat exchange with room air, and a flow rate control device for controlling a flow rate of the refrigerant, and a hybrid heat exchange part for making the outdoor heat exchange part and the indoor heat exchange part, which are independent from each other, to heat exchange with each other.

Abstract: Disclosed is a structure of a window frame used in apartments, detached dwellings, apartment units in a private house, residential/commercial combined buildings, or the like. The structure comprises an upper window frame (8) having at least one recess portion fixedly secured to a concrete casting surface of a ceiling (7), a lower window frame (9) having at least one recess portion secured fixed to a concrete casting surface of floor to be flush with the concrete casting surface of the floor, an interior window (2?) having both ends inserted into the upper and lower window frames to form a “”-shaped cross section, and an exterior window (3?) arranged apart from the interior window at predetermined intervals and having both ends inserted into the upper and lower window frames to form a “”-shaped cross section.

Abstract: An end plate for heat exchangers, includes a plurality of bodies and a connecting part. Each of the plurality of bodies has a plurality of holes to allow a refrigerant pipe to pass through the plurality of bodies. The connecting part connects the plurality of bodies to each other, with a recess being provided on the connecting part to allow the connecting part to be easily bent. A manufacturing method includes preparing a plurality of fins arranged to provide two or more parallel rows of fin arrays, preparing an end plate provided on a side of the fin arrays to connect the fin arrays to each other, inserting a refrigerant pipe into the fin arrays and the end plate to provide an assembly including the refrigerant pipe, the fin arrays, and the end plate, and bending the assembly at a predetermined angle around the connecting part of the end plate.

Abstract: Each object (such as for example an integrated circuit) of a population of similar objects is configured to generate instances of a dynamic binary identification code (ID) that differ from instances of IDs generated by all other member objects of the population. While bits residing in most of the bit positions of the ID generated by each member object of the population do not vary in state from instance-to-instance of that ID, bits residing in one or more of the bit positions of the ID may vary (drift) in state from instance-to-instance of that ID. A set of instances of the ID generated by each member object of the population are analyzed to construct a separate “drift profile” for each member object's ID indicating for each bit position a probability that the bit position will contain a bit of a particular state.

Abstract: A database system accesses database records referenced by a binary number key having two fields, a typeID field containing only deterministic bits, and a uniqueID field permissibly containing one or more non-deterministic bits at any bit positions therein. The database system maintains a set of databases, each being identified by a separate value of the typeID field of the binary number key. The records of each database are allocated among a plurality of bins, with each bin being identified (keyed) by separate value of a binID field, and with each record being identified (keyed) by a separate value of a recID field. The database system locates a record of interest referenced by the binary number key by first selecting a particular one of the databases that is identified by the typeID field of the binary number key.

Abstract: An improved structure of a handle for a re-writing device is disclosed. The handle is characterized in that an engaging hole for the handle is provided at an appropriate position on the operation panel of the device to provide horizontal insertion of the handle and to withdraw the handle from the engaging hole, the end face of the handle, which is at a furthest distance away from the handle mount base, is exposed on the surface of the operation panel and the main body of the handle is concealed within the re-writing device and the two lateral widths of frame seat of the individual re-writing device slightly clips to the two side walls of the handle and the corners of the lateral side of the handle mount base are provided with a sliding block and a sliding slot is provided to the frame seat lateral wall corresponding to the sliding block such that the sliding block is engaged with the sliding slot and is driven by the withdrawing direction of the handle.

Abstract: Each object (such as for example an integrated circuit) of a population of similar objects is configured to generate instances of a dynamic binary identification code (ID) that differ from instances of IDs generated by all other member objects of the population. While bits residing in most of the bit positions of the ID generated by each member object of the population do not vary in state from instance-to-instance of that ID, bits residing in one or more of the bit positions of the ID may vary (drift) in state from instance-to-instance of that ID. A set of instances of the ID generated by each member object of the population are analyzed to construct a separate “drift profile” for each member object's ID indicating for each bit position a probability that the bit position will contain a bit of a particular state.

Abstract: An improved structure of a handle for a re-writing device is disclosed. The handle is characterized in that an engaging hole for the handle is provided at an appropriate position on the operation panel of the device to provide horizontal insertion of the handle and to withdraw the handle from the engaging hole, the end face of the handle, which is at a furthest distance away from the handle mount base, is exposed on the surface of the operation panel and the main body of the handle is concealed within the re-writing device and the two lateral widths of frame seat of the individual re-writing device slightly clips to the two side walls of the handle and the corners of the lateral side of the handle mount base are provided with a sliding block and a sliding slot is provided to the frame seat lateral wall corresponding to the sliding block such that the sliding block is engaged with the sliding slot and is driven by the withdrawing direction of the handle.

Abstract: A crosspoint switch routes signals between its terminals in routing patterns defined by routing data from a host controller. The crosspoint switch includes an array of pass transistors. Each pass transistor, when turned on, provides a signal path interconnecting a separate, unique pair of the switch terminals. The crosspoint switch also includes two static random access memory banks. Each memory bank stores routing data defining a separate routing pattern and produces a separate set of output signals reflecting its stored data. A multiplexer delivers the output signals of a selected one of the memory banks to the switch array for controlling its pass transistors so that the switch array implements the routing pattern defined by the data in the selected memory bank. By loading routing data defining different routing patterns into the two memory banks, a host controller can thereafter quickly make the crosspoint switch alternate between the two routing patterns by toggling the multiplexer's control input.

Abstract: An electronic crossbar switch employs a switch array for selectively routing digital and analog signals between its terminals. A separate port for each terminal provides a path for digital and analog signals flowing in and out of the switch. Each port can be configured to operate with or without tristate buffering under control of a tristate control signal, to optionally latch input or output signals in response to clock and clock enable signals, and to buffer signals passing in or out of the switch terminal with or without an input direction control signal. A set of control inputs are provided in common to all ports, allowing an external host to transmit control signals in parallel to each port. Each port may be programmed to select any of its control inputs as its tristate, clock enable, clocking or direction control signal.

Abstract: An electronic crossbar switch employs a switch array for selectively routing signals between its terminals. A separate port provided for each terminal buffers signals flowing in and out of the switch. Each port can be configured to operate with or without tristate buffering under control of a tristate control signal, to optionally latch input or output signals in response to clock and clock enable signals, and to buffer signals passing in or out of the switch terminal in response to a direction control signal. A set of control inputs are provided in common to all ports, allowing an external host to transmit control signals in parallel to each port. Each port may be programmed to select any of its control inputs as its tristate, clock enable, clocking or direction control signal. A parallel "key" bus is also provided in common to all ports for conveying a key address from the host controller.

Abstract: A field programmable interconnect device (FPID) selectively routes signals between signal ports in response to commands from a host controller. Each command includes an address and data. The FPID includes an array of switch cells, each interconnecting a separate pair of the ports and each having first and second control signal inputs. When the first and second control signals are both asserted, the switch cell provides a signal path between the pair of the ports it interconnects. The FPID includes first and second sets of memory cells for storing data. Each first memory cell corresponds to a separate one of the switch cells and selectively asserts or deasserts the first control signal input to the corresponding switch cell according to its stored data. Each second memory cell corresponds to a separate group of switch cells and selectively asserts or deasserts the second control signal input to each switch cell of the corresponding group according to its stored data.

Abstract: A programmable backplane includes a motherboard having slots for receiving printed circuit boards (PCBs). A field programmable interconnect device (FPID) mounted on the motherboard includes a programmable crosspoint switch for selectively routing signals between terminals of the PCBs. The routing is determined by input programming data. The FPID bi-directionally buffers all signals passing between ports of the crosspoint switch and the PCB terminals and can alter signal routing dynamically in response to routing instructions generated by instruction sources mounted on or connected to the PCBs. The programmable backplane may be used as a communication hub in a communication network or parallel processing system.