Abstract: A method includes: receiving a design layout comprising a feature extending in a peripheral region and a central region of the design layout; determining compensation values associated with a pellicle assembly and the peripheral region according to an exposure distribution in an exposure field of a workpiece; and adjusting the design layout according to the compensation values. The modifying of the shape of the feature according to the compensation values includes: partitioning the peripheral region into compensation zones; and adjusting line widths in the compensation zones of the feature according to the compensation values associated with the respective compensation zones.

Abstract: A semiconductor structure includes a first interposer; a second interposer laterally adjacent to the first interposer, where the second interposer is spaced apart from the first interposer; and a first die attached to a first side of the first interposer and attached to a first side of the second interposer, where the first side of the first interposer and the first side of the second interposer face the first die.

Abstract: An integrated circuit includes an inductor that includes a first set of conductors in at least a first metal layer, and a guard ring enclosing the inductor. The guard ring includes a first conductor extending in a first direction, a second conductor extending in a second direction, and a first set of staggered conductors coupled to a first end of the first conductor and a first end of the second conductor. The first set of staggered conductors includes a second set of conductors in a second metal layer, a third set of conductors in a third metal layer and a first set of vias coupling the second set of conductors with the third set of conductors. The third metal layer is above the second metal layer. All metal lines in the second metal layer that are part of the guard ring extend in the first direction.

Abstract: A method includes: receiving a design layout comprising a feature extending in a peripheral region and a central region of the design layout; determining compensation values associated with a pellicle assembly and the peripheral region according to an exposure distribution in an exposure field of a workpiece; and adjusting the design layout according to the compensation values. The modifying of the shape of the feature according to the compensation values includes: partitioning the peripheral region into compensation zones, wherein the feature includes first portions disposed within the respective compensation zones and a second portion disposed within the central region; and reducing line widths of the first portions of the feature according to the compensation values associated with the respective compensation zones while keep the second portion of the feature uncompensated.

Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.

Abstract: A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.

Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.

Abstract: A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.

Abstract: A semiconductor structure includes a substrate including a first surface; a dielectric layer disposed over the first surface of the substrate; a first conductive line surrounded by the dielectric layer and extended over the first surface of the substrate; a second conductive line disposed adjacent to the first conductive line, surrounded by the dielectric layer and extended parallel to the first conductive line; a conductive via disposed over the first conductive line and extended through the dielectric layer; and a cross section of the conductive via substantially parallel to the first surface of the substrate, wherein the cross section of the conductive via is at least partially protruded from the first conductive line towards the second conductive line. Further, a method of manufacturing the semiconductor structure is also disclosed.

Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes the following operations. A first layout including a plurality of first features is provided. A modified second layout is determined. The modified second layout includes a plurality of modified features separated from each other, and each of the plurality of modified features respectively overlaps each of the plurality of first features. The modified second layout is outputted to a photomask.

Abstract: A semiconductor structure includes a substrate including a first surface; a dielectric layer disposed over the first surface of the substrate; a first conductive line surrounded by the dielectric layer and extended over the first surface of the substrate; a second conductive line disposed adjacent to the first conductive line, surrounded by the dielectric layer and extended parallel to the first conductive line; a conductive via disposed over the first conductive line and extended through the dielectric layer; and a cross section of the conductive via substantially parallel to the first surface of the substrate, wherein the cross section of the conductive via is at least partially protruded from the first conductive line towards the second conductive line. Further, a method of manufacturing the semiconductor structure is also disclosed.

Abstract: A method for manufacturing a semiconductor device is provided. The method includes providing a first layout including a plurality of first features and a second layout including a plurality of second features; shifting the second layout to generate a plurality of virtual layouts; comparing a score of each of the plurality of virtual layouts and determining a modified second layout having a target score out of the plurality of virtual layouts; and outputting the modified second layout to a photomask.

Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.

Abstract: A method includes: receiving a design layout comprising a feature extending in a peripheral region and a central region of the design layout; determining compensation values associated with a pellicle assembly and the peripheral region according to an exposure distribution in an exposure field of a workpiece; and adjusting the design layout according to the compensation values. The modifying of the shape of the feature according to the compensation values includes: partitioning the peripheral region into compensation zones, wherein the feature includes first portions disposed within the respective compensation zones and a second portion disposed within the central region; and reducing line widths of the first portions of the feature according to the compensation values associated with the respective compensation zones while keep the second portion of the feature uncompensated.

Abstract: A method, a non-transitory computer-readable storage medium and a system for adjusting a design layout are provided. The method includes: receiving a design layout including a feature in a peripheral region of the design layout; determining a first compensation value associated with the peripheral region according to an exposure distribution in an exposure field of a workpiece; and adjusting the design layout by modifying a shape of the feature according to the compensation value.

Abstract: Present disclosure provides a mask and a method for fabricating a semiconductor device, the mask includes a target pattern having consecutive edges, a first scattering bar and a second scattering bar extending along a primary direction and adjacent to consecutive edges of the target pattern, wherein the first scattering bar and the second scattering bar partially overlaps in the primary direction, and a connecting segment connecting between a first end of the first scattering bar and a first end of the second scattering bar, wherein the first scattering bar is not parallel to the connecting segment.

Abstract: A photolithographic mask assembly according to the present disclosure accompanies a photolithographic mask. The photolithographic mask includes a capping layer over a substrate and an absorber layer disposed over the capping layer. The absorber layer includes a first main feature area, a second main feature area, and a venting feature area disposed between the first main feature area and the second main feature area. The venting feature area includes a plurality of venting features.

Abstract: Present disclosure provide a method for fabricating a mask, including obtaining a target pattern to be imaged onto a substrate, providing a first scattering bar and a second scattering bar adjacent to consecutive edges of the target pattern, identifying a first length of the first scattering bar and a second length of the second scattering bar, connecting the first scattering bar and the second scattering bar when any of the first length and the second length is smaller than a predetermined value, identifying a separation between the first scattering bar and the second scattering bar subsequent to identifying the first length and the second length, disposing the first scattering bar and the second scattering bar in a first fashion when the separation is equal to zero, and disposing the first scattering bar and the second scattering bar in a second fashion when the separation is greater than zero.

Abstract: A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.