Patents by Inventor Chi-Ta Lu
Chi-Ta Lu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11055464Abstract: A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.Type: GrantFiled: October 30, 2018Date of Patent: July 6, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Ta Lu, Chi-Ming Tsai
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Publication number: 20210116804Abstract: A method for manufacturing a semiconductor device is provided. The method includes providing a first layout including a plurality of first features and a second layout including a plurality of second features; shifting the second layout to generate a plurality of virtual layouts; comparing a score of each of the plurality of virtual layouts and determining a modified second layout having a target score out of the plurality of virtual layouts; and outputting the modified second layout to a photomask.Type: ApplicationFiled: December 8, 2020Publication date: April 22, 2021Inventors: WEI-CHUNG HU, CHI-TA LU, CHI-MING TSAI
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Publication number: 20210064808Abstract: A method, a non-transitory computer-readable storage medium and a system for adjusting a design layout are provided. The method includes: receiving a design layout including a feature in a peripheral region of the design layout; determining a first compensation value associated with the peripheral region according to an exposure distribution in an exposure field of a workpiece; and adjusting the design layout by modifying a shape of the feature according to the compensation value.Type: ApplicationFiled: July 23, 2020Publication date: March 4, 2021Inventors: CHI-TA LU, CHIA-HUI LIAO, YIHUNG LIN, CHI-MING TSAI
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Publication number: 20210005552Abstract: A semiconductor structure includes a substrate including a first surface; a dielectric layer disposed over the first surface of the substrate; a first conductive line surrounded by the dielectric layer and extended over the first surface of the substrate; a second conductive line disposed adjacent to the first conductive line, surrounded by the dielectric layer and extended parallel to the first conductive line; a conductive via disposed over the first conductive line and extended through the dielectric layer; and a cross section of the conductive via substantially parallel to the first surface of the substrate, wherein the cross section of the conductive via is at least partially protruded from the first conductive line towards the second conductive line. Further, a method of manufacturing the semiconductor structure is also disclosed.Type: ApplicationFiled: September 20, 2020Publication date: January 7, 2021Inventors: CHI-TA LU, CHI-MING TSAI
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Patent number: 10877380Abstract: A method of generating an integrated circuit includes: receiving, by a processor, a first IC design layout; replacing, by the processor, a specific region in the first IC design layout with a first difference region; performing, by the processor, an inverse lithography technology process upon a junction region between the first difference region and the first IC design layout to generate a mask data; and causing the IC to be fabricated according to the mask data.Type: GrantFiled: September 17, 2019Date of Patent: December 29, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Yihung Lin, Yi-Feng Lu, Huang-Ming Wu, Chi-Ta Lu
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Patent number: 10866508Abstract: A method for manufacturing a photomask is provided. The method includes generating a plurality of virtual layouts; calculating a score for each of the plurality of virtual layouts in accordance with a total overlay area; comparing the scores of the plurality of virtual layouts and determining a modified layout having a target score out of the plurality of virtual layouts; and outputting the modified layout to a photomask. Each of the virtual layouts includes a plurality of the shifted features. A semiconductor manufacturing method is also provided.Type: GrantFiled: November 7, 2018Date of Patent: December 15, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Wei-Chung Hu, Chi-Ta Lu, Chi-Ming Tsai
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Patent number: 10784196Abstract: A semiconductor structure includes a substrate including a first surface; a dielectric layer disposed over the first surface of the substrate; a first conductive line surrounded by the dielectric layer and extended over the first surface of the substrate; a conductive via disposed over the first conductive line and extended through the dielectric layer; and a cross section of the conductive via parallel to the first surface of the substrate, wherein the first conductive line includes a second surface at least partially interfaced with the conductive via, the second surface of the first conductive line includes a first end, a second end opposite to the first end and a first central axis passing through the first end and the second end, the cross section of the conductive via includes a second central axis parallel to the first central axis and a third central axis orthogonal to the second central axis.Type: GrantFiled: December 6, 2018Date of Patent: September 22, 2020Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: Chi-Ta Lu, Chi-Ming Tsai
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Publication number: 20200098689Abstract: A semiconductor structure includes a substrate including a first surface; a dielectric layer disposed over the first surface of the substrate; a first conductive line surrounded by the dielectric layer and extended over the first surface of the substrate; a conductive via disposed over the first conductive line and extended through the dielectric layer; and a cross section of the conductive via parallel to the first surface of the substrate, wherein the first conductive line includes a second surface at least partially interfaced with the conductive via, the second surface of the first conductive line includes a first end, a second end opposite to the first end and a first central axis passing through the first end and the second end, the cross section of the conductive via includes a second central axis parallel to the first central axis and a third central axis orthogonal to the second central axis.Type: ApplicationFiled: December 6, 2018Publication date: March 26, 2020Inventors: CHI-TA LU, CHI-MING TSAI
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Publication number: 20200057833Abstract: A method includes receiving a pattern layout for a mask, shrinking the pattern layout to form a shrunk pattern, determining centerlines for each of a plurality of features within the shrunk pattern, and snapping the centerline for each of the plurality of features to a grid. The grid represents a minimum resolution size of a mask fabrication tool. The method further includes, after snapping the centerline for each of the plurality of features to the grid, fabricating the mask with the shrunk pattern.Type: ApplicationFiled: October 30, 2018Publication date: February 20, 2020Inventors: Chi-Ta Lu, Chi-Ming Tsai
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Publication number: 20200004136Abstract: Present disclosure provide a method for fabricating a mask, including obtaining a target pattern to be imaged onto a substrate, providing a first scattering bar and a second scattering bar adjacent to consecutive edges of the target pattern, identifying a first length of the first scattering bar and a second length of the second scattering bar, connecting the first scattering bar and the second scattering bar when any of the first length and the second length is smaller than a predetermined value, identifying a separation between the first scattering bar and the second scattering bar subsequent to identifying the first length and the second length, disposing the first scattering bar and the second scattering bar in a first fashion when the separation is equal to zero, and disposing the first scattering bar and the second scattering bar in a second fashion when the separation is greater than zero.Type: ApplicationFiled: January 22, 2019Publication date: January 2, 2020Inventors: HUANG-MING WU, JIUN-HAO LIN, JIA-GUEI JOU, CHI-TA LU, CHI-MING TSAI
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Publication number: 20190354006Abstract: A method for manufacturing a photomask is provided. The method includes generating a plurality of virtual layouts; calculating a score for each of the plurality of virtual layouts in accordance with a total overlay area; comparing the scores of the plurality of virtual layouts and determining a modified layout having a target score out of the plurality of virtual layouts; and outputting the modified layout to a photomask. Each of the virtual layouts includes a plurality of the shifted features. A semiconductor manufacturing method is also provided.Type: ApplicationFiled: November 7, 2018Publication date: November 21, 2019Inventors: WEI-CHUNG HU, CHI-TA LU, CHI-MING TSAI
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Patent number: 9136092Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a main feature; performing an optical proximity correction (OPC) process to the design layout; and thereafter, performing a jog reduction process to the design layout such that jog features of the design layout are reduced.Type: GrantFiled: April 9, 2012Date of Patent: September 15, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Ta Lu, Jia-Guei Jou, Yi-Hsien Chen, Peng-Ren Chen, Dong-Hsu Cheng
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Patent number: 8650511Abstract: The present disclosure provides for many different embodiments. A mask fabrication method and system is provided. The method and system identify critical areas of an integrated circuit (IC) design layout that has undergone optical proximity correction. The critical areas are areas of the OPCed IC design layout that are at risk for hot spots. A lithography process check is then performed on the critical areas of the OPCed IC design layout.Type: GrantFiled: April 30, 2010Date of Patent: February 11, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Ta Lu, Peng-Ren Chen, Dong-Hsu Cheng, Chang-Jyh Hsieh
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Publication number: 20130268901Abstract: The present disclosure provides one embodiment of an integrated circuit (IC) method. The method includes receiving an IC design layout having a main feature; performing an optical proximity correction (OPC) process to the design layout; and thereafter, performing a jog reduction process to the design layout such that jog features of the design layout are reduced.Type: ApplicationFiled: April 9, 2012Publication date: October 10, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Ta Lu, Jia-Guei Jou, Yi-Hsien Chen, Peng-Ren Chen, Dong-Hsu Cheng
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Patent number: 8458631Abstract: The present disclosure provides for methods of reducing cycle time in data preparation. In one embodiment, a method includes receiving an initial integrated circuit (IC) design layout and an optical proximity correction (OPC)-processed initial IC design layout, and receiving a revised IC design layout. The method further includes comparing the revised IC design layout to the initial IC design layout to identify a difference region of the revised IC design layout from the initial IC design layout, performing an OPC on the difference region of the revised IC design layout, and merging the OPC-processed difference region of the revised IC design layout with the OPC-processed initial IC design layout.Type: GrantFiled: August 11, 2011Date of Patent: June 4, 2013Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Ta Lu, Jia-Guei Jou, Peng-Ren Chen, Dong-Hsu Cheng
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Publication number: 20130042210Abstract: The present disclosure provides for methods of reducing cycle time in data preparation. In one embodiment, a method includes receiving an initial integrated circuit (IC) design layout and an optical proximity correction (OPC)-processed initial IC design layout, and receiving a revised IC design layout. The method further includes comparing the revised IC design layout to the initial IC design layout to identify a difference region of the revised IC design layout from the initial IC design layout, performing an OPC on the difference region of the revised IC design layout, and merging the OPC-processed difference region of the revised IC design layout with the OPC-processed initial IC design layout.Type: ApplicationFiled: August 11, 2011Publication date: February 14, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Ta Lu, Jia-Guei Jou, Peng-Ren Chen, Dong-Hsu Cheng
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Publication number: 20110271239Abstract: The present disclosure provides for many different embodiments. A mask fabrication method and system is provided. The method and system identify critical areas of an integrated circuit (IC) design layout that has undergone optical proximity correction. The critical areas are areas of the OPCed IC design layout that are at risk for hot spots. A lithography process check is then performed on the critical areas of the OPCed IC design layout.Type: ApplicationFiled: April 30, 2010Publication date: November 3, 2011Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chi-Ta Lu, Peng-Ren Chen, Dong-Hsu Cheng, Chang-Jyh Hsieh