Patents by Inventor Chi Wang

Chi Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230206481
    Abstract: A system and method for measuring circumference of human body are provided. The system includes a 3D sensor configured to obtain a 3D information of a human body with a garment on; a temperature sensor configured to obtain a thermal information of the human body with the garment on; a calibration unit configured to obtain a calibration parameter of the 3D sensor and the temperature sensor; a model generation unit configured to integrate the 3D information and the temperature information according to the calibration parameter to generate a 3D temperature model of the human body with the garment on; and a circumference computation unit configured to retrieve an original profile information corresponding to a target location from the 3D temperature model, and correct the original profile information according to a thermal compensation mechanism to obtain a real circumference of the human body corresponding to the target location.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Shang-Yi LIN, Tung-Fa LIOU, Chuan-Chi WANG
  • Publication number: 20230203415
    Abstract: A cell and tissue sheet forming package includes a container body, a membrane, a sliding door plate and a sealing film. The sliding door plate is disposed slidably on a top of the container body to cover or expose the membrane. The sliding door plate has a hole and a passive magnetic assembly. The cell injection equipment includes a carrier, an injection mechanism and a drive mechanism. The carrier carries the package, and the drive mechanism moves the carrier and the injection mechanism to have the injection mechanism to inject a solution, through the hole, into the package. A heating element of the carrier is introduced to heat the membrane and the solution to transform the solution into a colloid sheet on the membrane. Then, the positive magnetic assembly engages magnetically the passive magnetic assembly to slide the sliding door plate to expose the colloid sheet on the membrane.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: HSIN-YI HSU, YANG-CHENG LIN, CHAO-HONG HSU, YU-BING LIOU, LI-HSIN LIN, HSIN-HSIN SHEN, YU-CHI WANG, CHANG-CHOU LI, CHIH-HUNG HUANG
  • Publication number: 20230196626
    Abstract: A three-dimensional data encoding method includes: dividing three-dimensional points included in three-dimensional data into three-dimensional point sub-clouds including a first three-dimensional point sub-cloud and a second three-dimensional point sub-cloud; appending first information indicating a space of the first three-dimensional point sub-cloud to a header of the first three-dimensional point sub-cloud, and appending second information indicating a space of the second three-dimensional point sub-cloud to a header of the second three-dimensional point sub-cloud; and encoding the first three-dimensional point sub-cloud and the second three-dimensional point sub-cloud so that the first three-dimensional point sub-cloud and the second three-dimensional point sub-cloud are decodable independently of each other.
    Type: Application
    Filed: February 24, 2023
    Publication date: June 22, 2023
    Inventors: Chi WANG, Pongsak LASANG, Chung Dean HAN, Toshiyasu SUGIO
  • Publication number: 20230188705
    Abstract: A three-dimensional data encoding method includes: encoding a first flag indicating whether a node having a parent node different from a parent node of a current node is to be referred to in encoding of the current node included in an n-ary tree structure of three-dimensional points included in three-dimensional data; selecting a coding table from N coding tables according to occupancy states of neighboring nodes of the current node, and performing arithmetic encoding on information of the current node using the coding table selected, when the first flag indicates that the node is to be referred to; and selecting a coding table from M coding tables according to the occupancy states of the neighboring nodes of the current node, and performing arithmetic encoding on information of the current node using the coding table selected, when the first flag indicates that the node is not to be referred to.
    Type: Application
    Filed: February 6, 2023
    Publication date: June 15, 2023
    Inventors: Toshiyasu SUGIO, Chi WANG, Pongsak LASANG, Chung Dean HAN, Noritaka IGUCHI
  • Patent number: 11672853
    Abstract: Immunogenic compositions comprising partially glycosylated viral glycoproteins for use as vaccines against viruses are provided. Vaccines formulated using mono-, di-, or tri-glycosylated viral surface glycoproteins and polypeptides provide potent and broad protection against viruses, even across strains. Pharmaceutical compositions comprising monoglycosylated hemagglutinin polypeptides and vaccines generated therefrom and methods of their use for prophylaxis or treatment of viral infections are disclosed. Methods and compositions are disclosed for influenza virus HA, NA and M2, RSV proteins F, G and SH, Dengue virus glycoproteins M or E, hepatitis C virus glycoprotein E1 or E2 and HIV glycoproteins gp120 and gp41.
    Type: Grant
    Filed: June 4, 2019
    Date of Patent: June 13, 2023
    Assignee: Academia Sinica
    Inventors: Chi-Huey Wong, Che Ma, Cheng-Chi Wang, Juine-Ruey Chen
  • Patent number: 11677981
    Abstract: A three-dimensional data encoding method includes: generating a bitstream by encoding subspaces included in a current space in which three-dimensional points are included. The bitstream includes encoded data respectively corresponding to the subspaces. In the generating of the bitstream, a list of information about the subspaces is stored in first control information included in the bitstream. The subspaces are respectively associated with identifiers assigned to the subspaces, and the first control information is common to the encoded data. Each of the identifiers assigned to the subspaces respectively corresponding to the encoded data is stored in a header of a corresponding one of the encoded data.
    Type: Grant
    Filed: October 4, 2021
    Date of Patent: June 13, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Chung Dean Han, Pongsak Lasang, Chi Wang, Noritaka Iguchi, Toshiyasu Sugio
  • Patent number: 11671056
    Abstract: A crystal oscillator and a phase noise reduction method thereof are provided. The crystal oscillator may include a crystal oscillator core circuit, a first bias circuit and a phase noise reduction circuit, the first bias circuit is coupled to an output terminal of the crystal oscillator core circuit, and the phase noise reduction circuit is coupled to the output terminal of the crystal oscillator core circuit. In operations of the crystal oscillator, the crystal oscillator core circuit is configured to generate a sinusoidal wave. The first bias circuit is configured to provide a first voltage level to be a bias voltage of the sinusoidal wave. The phase noise reduction circuit is configured to reset the bias voltage of the sinusoidal wave in response to a voltage level of the sinusoidal wave exceeding a specific voltage range. For example, the specific voltage range is determined according to a second voltage level.
    Type: Grant
    Filed: March 14, 2022
    Date of Patent: June 6, 2023
    Assignee: MEDIATEK INC.
    Inventors: Sen-You Liu, Chien-Wei Chen, Keng-Meng Chang, Yao-Chi Wang
  • Patent number: 11670650
    Abstract: A semiconductor device includes a first semiconductor structure and a second semiconductor structure. The first semiconductor structure includes silicon. The second semiconductor structure is embedded in the first semiconductor structure, in which the second semiconductor structure has at least one convex portion and at least one concave portion. The convex portion and the concave portion are on at least one edge of the second semiconductor structure, and a shape of the concave portion includes rectangle, trapezoid, inverted trapezoid, or parallelogram. The second semiconductor structure includes germanium, elements of group III or group V, or combinations thereof.
    Type: Grant
    Filed: June 5, 2020
    Date of Patent: June 6, 2023
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Zong-Jie Wu, Chiao-Chi Wang, Chung-Chuan Tseng, Chia-Ping Lai
  • Patent number: 11661783
    Abstract: This disclosure is directed to an electric support rod having a driving assembly, an actuating assembly, and a bearing. The driving assembly has a first outer tube and a driving unit in the first outer tube. An internal thread is configured in the first outer tube. The actuating assembly has a second outer tube and a transmission screw rod in the second outer tube. Multiple elastic arms axially are extended from the second outer tube and arranged spacedly around the transmission screw rod. Each elastic arm has an outer thread structure and a hook portion. The second outer tube is inserted in the first outer tube, the internal thread is screwed with the outer thread structure. One end of the transmission screw rod protrudes from the second outer tube to engage the driving unit. The bearing sheathes the transmission screw rod and the hook portion latches the bearing.
    Type: Grant
    Filed: March 1, 2022
    Date of Patent: May 30, 2023
    Assignees: HSIN CHONG MACHINERY WORKS CO. LTD., FUZHOU MINGFANG AUTOMOBILE PARTS INDUSTRY CO., LTD.
    Inventors: Chi-Wang Wu, Feng-Lin Yang, Jeffrey Chung-Chiang Hsi
  • Patent number: 11664426
    Abstract: A semiconductor device includes an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride.
    Type: Grant
    Filed: March 3, 2022
    Date of Patent: May 30, 2023
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Yu-Ming Hsu, Yu-Chi Wang, Yen-Hsing Chen, Tsung-Mu Yang, Yu-Ren Wang
  • Publication number: 20230155301
    Abstract: An antenna module includes a feeding end, multiple first forked radiators, and multiple connecting parts. The first forked radiators are disposed side by side. The connecting parts respectively extend from the feeding end to the first forked radiators. The feeding end, the first forked radiators, and the connecting parts are located on a same plane. The antenna module resonates at a frequency band, and a path length from the feeding end to an end of each of the forked radiators through the corresponding connecting part is ¼ wavelength of the frequency band.
    Type: Application
    Filed: September 8, 2022
    Publication date: May 18, 2023
    Applicant: PEGATRON CORPORATION
    Inventors: Chien-Yi Wu, Wu-Hua Chen, I-Shu Lee, Hung-Ming Yu, Chao-Hsu Wu, Yung-Yi Lee, Man-Jung Tsao, Chi-Min Tang, Shao-Chi Wang
  • Publication number: 20230150903
    Abstract: The present invention provides a method for preparing 2,2-bis(4-hydroxycyclohexyl)propane, comprising: hydrogenating a reactive solution containing 2,2-bis(4-hydroxyphenyl)propane under a hydrogen atmosphere in a reactor with catalyst within a temperature range of 80-165° C. and a pressure range of 85-110 kg/cm2 to prepare the 2,2-bis(4-hydroxycyclohexyl)propane. The method of present invention has an advantage of high yield properties and achieves mass production easily, thereby enhancing the value of the industrial application.
    Type: Application
    Filed: June 14, 2022
    Publication date: May 18, 2023
    Applicant: CHINA PETROCHEMICAL DEVELOPMENT CORPORATION, TAIPEI (TAIWAN)
    Inventors: Yi-Chi WANG, Hsin-Wei CHANG, Weng-Keong TANG, Chia-Hui SHEN
  • Publication number: 20230141735
    Abstract: A loop filter utilized in an encoder includes a constrained directional enhancement filter and a decision circuit. The constrained directional enhancement filter is arranged to process multiple frames, wherein for a first frame in the multiple frames, the constrained directional enhancement filter determines a best filter strength of each block in the first frame in a first filter strength list, and determines a second filter strength list according to content of the first frame. The decision circuit is coupled to the constrained directional enhancement filter, and is arranged to record which index in the first filter strength list is the best filter strength corresponding to each block in the first frame, and provide the first filter strength list and the index corresponding to each block to an encoding circuit of the encoder as an output of the encoder.
    Type: Application
    Filed: November 11, 2021
    Publication date: May 11, 2023
    Applicant: Realtek Semiconductor Corp.
    Inventors: Weimin Zeng, Chi-Wang Chai, Wei Li, Rong Zhang, Wujun Chen
  • Publication number: 20230141458
    Abstract: A three-dimensional data encoding method includes encoding information of a current node included in an N-ary tree structure of three-dimensional points included in three-dimensional data, where N is an integer greater than or equal to 2. In the encoding, first information is encoded, the first information indicating a range for one or more referable neighboring nodes among neighboring nodes spatially neighboring the current node, and the current node is encoded with reference to a neighboring node within the range.
    Type: Application
    Filed: December 30, 2022
    Publication date: May 11, 2023
    Inventors: Chi WANG, Pongsak LASANG, Chung Dean HAN, Toshiyasu SUGIO
  • Publication number: 20230129218
    Abstract: An electronic device including a connection element is provided. The connection element includes a first insulation layer and a second insulation layer. The first insulation layer has a first opening. A sidewall of the first insulation layer at the first opening has roughness different from roughness of a top surface of the first insulation layer. The second insulation layer is disposed on the first insulation layer, and the second insulation layer has a second opening. The sidewall of the first insulation layer at the first opening is exposed by the second opening. A method of fabricating an electronic device is also provided.
    Type: Application
    Filed: May 18, 2022
    Publication date: April 27, 2023
    Applicant: Innolux Corporation
    Inventors: Chin-Lung Ting, Ker-Yih Kao, Cheng-Chi Wang, Kuang-Ming Fan, Chun-Hung Chen, Wen-Hsiang Liao, Ming-Hsien Shih
  • Publication number: 20230126461
    Abstract: A method for calculating an object pick-and-place sequence and an electronic apparatus for automatic storage pick-and-place are provided. When a warehousing operation is to be performed, the following steps are performed. A weight of an object to be stocked that is to be put on a shelf is obtained. The weight is substituted into a plurality of coordinate positions corresponding to a plurality of unused grid positions respectively, so as to calculate a plurality of estimated center of gravity positions. Whether the estimated center of gravity positions are located within a balance standard area is determined so as to sieve out a plurality of candidate grid positions from these unused grid positions. One of the candidate grid positions is selected as a recommended position of the object to be stocked.
    Type: Application
    Filed: July 13, 2022
    Publication date: April 27, 2023
    Applicant: GlobalWafers Co., Ltd.
    Inventors: Chia-Lin Li, Shang-Chi Wang, Chi Yuan Hsu, Han-Zong Wu
  • Publication number: 20230117955
    Abstract: An electronic device including a connection element is provided. The connection element includes a first metal layer, a first insulation layer, and a second insulation layer. The first insulation layer is disposed on the first metal layer and has a first hole and a second hole. The second insulation layer is disposed on the first insulation layer. The first hole exposes a portion of the first metal layer, and the second insulation layer extends into the second hole. A method of fabricating an electronic device is also provided.
    Type: Application
    Filed: May 18, 2022
    Publication date: April 20, 2023
    Applicant: Innolux Corporation
    Inventors: Chin-Lung Ting, Ker-Yih Kao, Cheng-Chi Wang, Kuang-Ming Fan, Chun-Hung Chen, Wen-Hsiang Liao, Ming-Hsien Shih
  • Patent number: 11625865
    Abstract: A three-dimensional data encoding method includes: dividing three-dimensional points included in three-dimensional data into three-dimensional point sub-clouds including a first three-dimensional point sub-cloud and a second three-dimensional point sub-cloud; appending first information indicating a space of the first three-dimensional point sub-cloud to a header of the first three-dimensional point sub-cloud, and appending second information indicating a space of the second three-dimensional point sub-cloud to a header of the second three-dimensional point sub-cloud; and encoding the first three-dimensional point sub-cloud and the second three-dimensional point sub-cloud so that the first three-dimensional point sub-cloud and the second three-dimensional point sub-cloud are decodable independently of each other.
    Type: Grant
    Filed: September 30, 2020
    Date of Patent: April 11, 2023
    Assignee: PANASONIC INTELLECTUAL PROPERTY CORPORATION OF AMERICA
    Inventors: Chi Wang, Pongsak Lasang, Chung Dean Han, Toshiyasu Sugio
  • Patent number: 11626442
    Abstract: Various embodiments of the present disclosure are directed towards methods for forming an image sensor in which a device layer overlies and has a different semiconductor material than a substrate and in which the device layer has high crystalline quality. Some embodiments of the methods include: epitaxially growing the device layer on the substrate; patterning the device layer to form a trench dividing the device layer into mesa structures corresponding to pixels; forming an inter-pixel dielectric layer filling the trench and separating the mesa structures; and forming photodetectors in the mesa structures. Other embodiments of the methods include: depositing the inter-pixel dielectric layer over the substrate; patterning the inter-pixel dielectric layer to form cavities corresponding to the pixels; epitaxially growing the mesa structures in the cavities; and forming the photodetectors in the mesa structures.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: April 11, 2023
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chiao-Chi Wang, Chung-Chuan Tseng, Chia-Ping Lai, Szu-Chien Tseng, Yeh-Hsun Fang
  • Patent number: 11626444
    Abstract: A semiconductor device with dummy and active pixel structures and a method of fabricating the same are disclosed. The semiconductor device includes a first pixel region with a first pixel structure, a second pixel region, surrounding the first pixel region, includes a second pixel structure adjacent to the first pixel structure and electrically isolated from the first pixel structure, and a contact pad region with a pad structure disposed adjacent to the second pixel region. The first pixel structure includes a first epitaxial structure disposed within a substrate and a first capping layer disposed on the first epitaxial structure. The second pixel structure includes a second epitaxial structure disposed within the substrate and a second capping layer disposed on the second epitaxial structure. Top surfaces of the first and second epitaxial structures are substantially coplanar with each other. The first and second epitaxial structures includes a same semiconductor material.
    Type: Grant
    Filed: August 27, 2020
    Date of Patent: April 11, 2023
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Yu-Wei Chen, Chung-Chuan Tseng, Chiao-Chi Wang, Chia-Ping Lai