Patents by Inventor Chi-Wei Lo

Chi-Wei Lo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240363400
    Abstract: A method for manufacturing a semiconductor device includes: forming a first feature and a second feature extending in a normal direction transverse to a substrate; directionally depositing a dielectric material upon the features at an inclined angle relative to the normal direction so as to form a cap layer including a top portion disposed on a top surface of each of the features, and two opposite wall portions extending downwardly from two opposite ends of the top portion to partially cover two opposite lateral surfaces of each of the features, respectively, the cap layer on the first feature being spaced apart from the cap layer on the second feature; forming a sacrificial feature in a recess between the features; forming a sustaining layer to cover the sacrificial feature; and removing the sacrificial feature to form an air gap.
    Type: Application
    Filed: July 5, 2024
    Publication date: October 31, 2024
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Chin LEE, Ting-Ya LO, Chi-Lin TENG, Cherng-Shiaw TSAI, Shao-Kuan LEE, Kuang-Wei YANG, Gary LIU, Hsin-Yen HUANG, Hsiao-Kang CHANG, Shau-Lin SHUE
  • Patent number: 12094764
    Abstract: A method for forming an interconnect structure is described. In some embodiments, the method includes forming a conductive layer, removing portions of the conductive layer to form a via portion extending upward from a bottom portion, forming a sacrificial layer over the via portion and the bottom portion, recessing the sacrificial layer to a level substantially the same or below a level of a top surface of the bottom portion, forming a first dielectric material over the via portion, the bottom portion, and the sacrificial layer, and removing the sacrificial layer to form an air gap adjacent the bottom portion.
    Type: Grant
    Filed: August 30, 2021
    Date of Patent: September 17, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Chin Lee, Hsiao-Kang Chang, Ting-Ya Lo, Chi-Lin Teng, Cherng-Shiaw Tsai, Shao-Kuan Lee, Kuang-Wei Yang, Hsin-Yen Huang, Shau-Lin Shue
  • Publication number: 20240301584
    Abstract: A process for cleaning a substrate includes removing carbon containing contaminants from a native oxide layer on a surface of a substrate by performing a reducing process using a hydrogen containing plasma, and after removing carbon containing contaminants, removing the native oxide layer from the substrate by performing an etch process using a fluorine containing plasma.
    Type: Application
    Filed: May 17, 2024
    Publication date: September 12, 2024
    Inventors: Christopher S. OLSEN, Theresa K. GUARINI, Jeffrey TOBIN, Lara HAWRYLCHAK, Peter STONE, Chi Wei LO, Saurabh CHOPRA
  • Patent number: 12062572
    Abstract: A method for manufacturing a semiconductor device includes: forming a first feature and a second feature extending in a normal direction transverse to a substrate; directionally depositing a dielectric material upon the features at an inclined angle relative to the normal direction so as to form a cap layer including a top portion disposed on a top surface of each of the features, and two opposite wall portions extending downwardly from two opposite ends of the top portion to partially cover two opposite lateral surfaces of each of the features, respectively, the cap layer on the first feature being spaced apart from the cap layer on the second feature; forming a sacrificial feature in a recess between the features; forming a sustaining layer to cover the sacrificial feature; and removing the sacrificial feature to form an air gap.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: August 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Chin Lee, Ting-Ya Lo, Chi-Lin Teng, Cherng-Shiaw Tsai, Shao-Kuan Lee, Kuang-Wei Yang, Gary Liu, Hsin-Yen Huang, Hsiao-Kang Chang, Shau-Lin Shue
  • Publication number: 20230324634
    Abstract: A miniature optoelectronic signal conversion and transmission device includes an optoelectronic signal module and an optical-fiber connector combined together. The optoelectronic signal module includes a silicon substrate that is electrically connected with a driver chip and an optoelectronic signal processor board arranged in a stacked package. The silicon substrate includes light-transmitting and light-receiving elements. Optical fibers provided in the optical-fiber connector have a signal receiving/transmitting terminal forming a refraction surface corresponding to and spaced from the light-transmitting and light-receiving elements. When an optical signal is transmitted through the optical fibers to the refraction surface, the optical signal is redirected for transmitting toward the light-transmitting and light-receiving elements.
    Type: Application
    Filed: April 11, 2022
    Publication date: October 12, 2023
    Inventors: Chi-Wei Lo, Jing-Qing Chan, Cheng-Hsin Kuo, Guan-Shiou Chen
  • Patent number: 11296189
    Abstract: A method for depositing a phosphorus doped silicon arsenide film is disclosed. The method may include, providing a substrate within a reaction chamber, heating the substrate to a deposition temperature, exposing the substrate to a silicon precursor, an arsenic precursor, and a phosphorus dopant precursor, and depositing the phosphorus doped silicon arsenide film over a surface of the substrate. Semiconductor device structures including a phosphorus doped silicon arsenide film deposited by the methods of the disclosure are also provided.
    Type: Grant
    Filed: September 1, 2020
    Date of Patent: April 5, 2022
    Assignee: ASM IP Holding B.V.
    Inventors: Chi-Wei Lo, Alexandros Demos, Raj Kumar
  • Patent number: 11091217
    Abstract: A joint structure of a composite bicycle frame includes a base layer and at least one reinforcing layer. The base layer is made of a first polymeric matrix material doped with a plurality of first fibers. The first fibers have random fiber orientation, and the base layer has a first thickness. The reinforcing layer is adhesively connected to the base layer. The reinforcing layer is made of a second polymeric matrix material doped with a plurality of second fibers. The second fibers have a single fiber orientation. The reinforcing layer has a second thickness which is smaller than the first thickness of the base layer.
    Type: Grant
    Filed: January 18, 2018
    Date of Patent: August 17, 2021
    Assignee: GIANT MANUFACTURING CO., LTD.
    Inventors: Chi-Wei Lo, Chih-Kai Chang, Hsu-Pin Hsin, Hung-Chikh Lai
  • Publication number: 20210010160
    Abstract: Embodiments of the present invention generally relate to methods for removing contaminants and native oxides from substrate surfaces. The methods generally include removing contaminants disposed on the substrate surface using a plasma process, and then cleaning the substrate surface by use of a remote plasma assisted dry etch process.
    Type: Application
    Filed: September 29, 2020
    Publication date: January 14, 2021
    Inventors: Christopher S. OLSEN, Theresa Kramer GUARINI, Jeffrey A. TOBIN, Lara HAWRYLCHAK, Peter STONE, Chi Wei LO, Saurabh CHOPRA
  • Publication number: 20200395444
    Abstract: A method for depositing a phosphorus doped silicon arsenide film is disclosed. The method may include, providing a substrate within a reaction chamber, heating the substrate to a deposition temperature, exposing the substrate to a silicon precursor, an arsenic precursor, and a phosphorus dopant precursor, and depositing the phosphorus doped silicon arsenide film over a surface of the substrate. Semiconductor device structures including a phosphorus doped silicon arsenide film deposited by the methods of the disclosure are also provided.
    Type: Application
    Filed: September 1, 2020
    Publication date: December 17, 2020
    Inventors: Chi-Wei Lo, Alexandros Demos, Raj Kumar
  • Patent number: 10837122
    Abstract: Embodiments of the present invention generally relate to methods for removing contaminants and native oxides from substrate surfaces. The methods generally include removing contaminants disposed on the substrate surface using a plasma process, and then cleaning the substrate surface by use of a remote plasma assisted dry etch process.
    Type: Grant
    Filed: August 26, 2019
    Date of Patent: November 17, 2020
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Christopher S. Olsen, Theresa K. Guarini, Jeffrey Tobin, Lara Hawrylchak, Peter Stone, Chi Wei Lo, Saurabh Chopra
  • Patent number: 10797133
    Abstract: A method for depositing a phosphorus doped silicon arsenide film is disclosed. The method may include, providing a substrate within a reaction chamber, heating the substrate to a deposition temperature, exposing the substrate to a silicon precursor, an arsenic precursor, and a phosphorus dopant precursor, and depositing the phosphorus doped silicon arsenide film over a surface of the substrate. Semiconductor device structures including a phosphorus doped silicon arsenide film deposited by the methods of the disclosure are also provided.
    Type: Grant
    Filed: June 21, 2018
    Date of Patent: October 6, 2020
    Assignee: ASM IP Holding B.V.
    Inventors: Chi-Wei Lo, Alexandros Demos, Raj Kumar
  • Publication number: 20190393308
    Abstract: A method for depositing a phosphorus doped silicon arsenide film is disclosed. The method may include, providing a substrate within a reaction chamber, heating the substrate to a deposition temperature, exposing the substrate to a silicon precursor, an arsenic precursor, and a phosphorus dopant precursor, and depositing the phosphorus doped silicon arsenide film over a surface of the substrate. Semiconductor device structures including a phosphorus doped silicon arsenide film deposited by the methods of the disclosure are also provided.
    Type: Application
    Filed: June 21, 2018
    Publication date: December 26, 2019
    Inventors: Chi-Wei Lo, Alexandros Demos, Raj Kumar
  • Publication number: 20190382917
    Abstract: Embodiments of the present invention generally relate to methods for removing contaminants and native oxides from substrate surfaces. The methods generally include removing contaminants disposed on the substrate surface using a plasma process, and then cleaning the substrate surface by use of a remote plasma assisted dry etch process.
    Type: Application
    Filed: August 26, 2019
    Publication date: December 19, 2019
    Inventors: Christopher S. OLSEN, Theresa K. GUARINI, Jeffrey TOBIN, Lara HAWRYLCHAK, Peter STONE, Chi Wei LO, Saurabh CHOPRA
  • Patent number: 10428441
    Abstract: Embodiments of the present invention generally relate to methods for removing contaminants and native oxides from substrate surfaces. The methods generally include removing contaminants disposed on the substrate surface using a plasma process, and then cleaning the substrate surface by use of a remote plasma assisted dry etch process.
    Type: Grant
    Filed: June 19, 2017
    Date of Patent: October 1, 2019
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Christopher S. Olsen, Theresa K. Guarini, Jeffrey Tobin, Lara Hawrylchak, Peter Stone, Chi Wei Lo, Saurabh Chopra
  • Patent number: 10374373
    Abstract: A connector fixing structure having a transmission plug and an adapter plug; wherein the transmission plug is respectively set with a first magnetic element, a guide slot, and a positioning groove; and the adapter plug is respectively set with a signal jack, a second magnetic element, a protruding block, and a resilient piece at the positions of the connection section. The first plug of small size set in the transmission plug can electrically connected with the signal jack. And, the first magnetic element and the second magnetic element can be mutually adsorbed, the protruding block can be mutually combined, and the positioning groove can be mutually engaged with the resilient piece. Therefore, the multi-point stable combination between the transmission plug and the adapter plug is achieved. It also enables the first plug to perform the connection ability after the second plug penetrates through the fitting hole of smaller size.
    Type: Grant
    Filed: March 21, 2018
    Date of Patent: August 6, 2019
    Inventor: Chi-Wei Lo
  • Patent number: 10283897
    Abstract: A fast connector pull-to-penetrate device includes a pull-through and penetration device that includes two flexible extension arms, each having a free end formed with a through aperture. A cap is formed with a coupling opening in each of two opposite sides thereof. The pull-through and penetration device is selectively fit to a transmission cable at an end of a connector and the cap is attached to the connector and fit to a signal terminal of the connector, such that the extension arms are respectively received through the coupling openings of the cap to have the through apertures moved past the two coupling openings and located frontward of the cap. A rope is tied to the through apertures of the extension arms to allow the pull-through and penetration device, to be moved through a number of installation holes through pulling of the rope.
    Type: Grant
    Filed: June 12, 2018
    Date of Patent: May 7, 2019
    Inventor: Chi-Wei Lo
  • Patent number: 10205208
    Abstract: A method and device for harvesting and storing solar energy is provided. The device converts solar energy to electrical energy via the photovoltaic effect. The device includes a pair of electrodes, at least one of which is transparent to allow solar energy to pass through. A medium is disposed between the electrodes which exhibits a combination of photovoltaic and ferroelectric properties. When solar energy passes through the transparent electrode and is received by the medium, electron-hole pairs establish a voltage potential between electrodes in the device via the photovoltaic effect. The voltage potential may be retained and the mobile charge may be stored in the absence of solar energy via the ferroelectric effect.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: February 12, 2019
    Assignee: Wisconsin Alumni Research Foundation
    Inventors: Hongrui Jiang, Chensha Li, Chi-Wei Lo
  • Publication number: 20180208265
    Abstract: A joint structure of a composite bicycle frame includes a base layer and at least one reinforcing layer. The base layer is made of a first polymeric matrix material doped with a plurality of first fibers. The first fibers have random fiber orientation, and the base layer has a first thickness. The reinforcing layer is adhesively connected to the base layer. The reinforcing layer is made of a second polymeric matrix material doped with a plurality of second fibers. The second fibers have a single fiber orientation. The reinforcing layer has a second thickness which is smaller than the first thickness of the base layer.
    Type: Application
    Filed: January 18, 2018
    Publication date: July 26, 2018
    Inventors: Chi-Wei LO, Chih-Kai CHANG, Hsu-Pin HSIN, Hung-Chikh LAI
  • Publication number: 20180170097
    Abstract: A carbon fiber wheel rim is disclosed. The carbon fiber wheel rim is corresponding disposed between two braking elements, and includes a rim body and a reinforcing layer. The rim body is made of a carbon fiber composites material. The reinforcing layer is disposed on a surface of the rim body, wherein the reinforcing layer is made of a fibrous veil having an isotropy.
    Type: Application
    Filed: May 8, 2017
    Publication date: June 21, 2018
    Inventors: Chi-Wei LO, Chih-Kai CHANG
  • Patent number: 9991876
    Abstract: A master-slave flip-flop includes a master latch, a slave latch, a first logic gate and a signal transition detector. The first logic gate is receiving a reference clock and a first control clock, and outputting a first trigger signal to control one of the master latch and the slave latch, which are connected with a logic circuit, to switch to an opaque state or a transparent state, wherein the other one of the master latch and the slave latch is switched to an opaque state or a transparent state according to the reference clock. The above-mentioned master-slave flip-flop can correct sampling when a timing error occurs.
    Type: Grant
    Filed: December 20, 2016
    Date of Patent: June 5, 2018
    Assignee: NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Shyh-Jye Jou, Chia-Hsiang Yang, Wei-Chang Liu, Chi-Wei Lo, Ching-Da Chan