Patents by Inventor Chi-Wei Wang
Chi-Wei Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240142270Abstract: A dynamic calibration method for heterogeneous sensors includes: sensing dynamic objects by a first sensor to generate first sensing data; sensing the dynamic objects by a second sensor to generate second sensing data; performing feature matching between the first sensing data and the second sensing data to determine first valid data and second valid data, and identifying a tracked object from the dynamic objects based on the first valid data and the second valid data; performing feature comparison between the first valid data and the second valid data corresponding to the tracked object to calculate data errors between the first sensor and the second sensor; and calculating a calibration parameter based on the first valid data and the second valid data when the number of the data errors exceeds an error threshold, and adjusting the first sensing data and the second sensing data based on the calibration parameter.Type: ApplicationFiled: January 12, 2023Publication date: May 2, 2024Applicant: Industrial Technology Research InstituteInventors: Po-Wei Chen, Chi-Hung Wang, Che-Jui Chang
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Patent number: 11970342Abstract: The present invention relates to a chip tray positioning device, which mainly comprises a frame body, a tray conveying module, a pulling module, a pushing module and a controller. The tray conveying module is disposed on the frame body, electrically connected to the controller and controlled to convey a chip tray from the start area to the end area. The pulling module and the pushing module are disposed on the frame body, electrically connected to the controller and controlled to cause the chip tray to be abutted against the end wall and the lateral wall of the frame body, thereby realizing the positioning of the chip tray and eliminating an error formed in the transfer process of the chip tray. In addition, the controller also controls the pushing module to knock the chip tray at a specific frequency so that the chip tray is vibrated.Type: GrantFiled: September 7, 2022Date of Patent: April 30, 2024Assignee: CHROMA ATE INC.Inventors: Chien-Ming Chen, Jui-Hsiung Chen, Chi-Wei Wang
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Publication number: 20240134691Abstract: A system allocates scratchpad memory (SPM) to heterogeneous devices for neural network computing. The system executes the operations of a global optimization manager. The global optimization manager receives compilation states from compilers, which compile corresponding subgraphs of a neural network model into corresponding subcommands that run on the heterogeneous devices. The global optimization manager unifies records of a same object across different ones of the compilation states, and allocates the SPM to the subgraphs according to the unified records of the compilation states.Type: ApplicationFiled: October 18, 2022Publication date: April 25, 2024Inventor: Chi-Wei Wang
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Patent number: 11964881Abstract: A method for making iridium oxide nanoparticles includes dissolving an iridium salt to obtain a salt-containing solution, mixing a complexing agent with the salt-containing solution to obtain a blend solution, and adding an oxidating agent to the blend solution to obtain a product mixture. A molar ratio of a complexing compound of the complexing agent to the iridium salt is controlled in a predetermined range so as to permit the product mixture to include iridium oxide nanoparticles.Type: GrantFiled: July 27, 2020Date of Patent: April 23, 2024Assignee: NATIONAL YANG MING CHIAO TUNG UNIVERSITYInventors: Pu-Wei Wu, Yi-Chieh Hsieh, Han-Yi Wang, Kuang-Chih Tso, Tzu-Ying Chan, Chung-Kai Chang, Chi-Shih Chen, Yu-Ting Cheng
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Patent number: 11961897Abstract: A first fin structure is disposed over a substrate. The first fin structure contains a semiconductor material. A gate dielectric layer is disposed over upper and side surfaces of the first fin structure. A gate electrode layer is formed over the gate dielectric layer. A second fin structure is disposed over the substrate. The second fin structure is physically separated from the first fin structure and contains a ferroelectric material. The second fin structure is electrically coupled to the gate electrode layer.Type: GrantFiled: January 10, 2022Date of Patent: April 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chi-Hsing Hsu, Sai-Hooi Yeong, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang, Min Cao
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Publication number: 20230089716Abstract: The present invention relates to a chip tray positioning device, which mainly comprises a frame body, a tray conveying module, a pulling module, a pushing module and a controller. The tray conveying module is disposed on the frame body, electrically connected to the controller and controlled to convey a chip tray from the start area to the end area. The pulling module and the pushing module are disposed on the frame body, electrically connected to the controller and controlled to cause the chip tray to be abutted against the end wall and the lateral wall of the frame body, thereby realizing the positioning of the chip tray and eliminating an error formed in the transfer process of the chip tray. In addition, the controller also controls the pushing module to knock the chip tray at a specific frequency so that the chip tray is vibrated.Type: ApplicationFiled: September 7, 2022Publication date: March 23, 2023Inventors: Chien-Ming CHEN, Jui-Hsiung CHEN, Chi-Wei WANG
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Patent number: 9898257Abstract: An automatic probe construction system and the method thereof are provided. The automatic probe construction system includes a data dereference analysis module, a probe selection module, and a probe verification module. The data dereference analysis module dereferences a plurality of target data of an electronic apparatus according to a plurality of pointers, and constructs a plurality of candidate probes. The probe selection module constructs a control flow graph according to the candidate probes and an instruction code of an executable image file, to select via the control flow graph from the candidate probes at least one dedicated probe. The probe verification module searches the executable image file for an instruction code corresponding to the dedicated probe, to verify the dedicated probe. Therefore, the dedicated probe can be constructed automatically, and the number of the dedicated probes is thus limited.Type: GrantFiled: February 4, 2016Date of Patent: February 20, 2018Assignee: NATIONAL CHIAO TUNG UNIVERSITYInventors: Shiuhpyng Shieh, Chi-Wei Wang, Chia-Wei Wang, Chia-Wei Hsu
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Patent number: 9747452Abstract: A method for determining whether a to-be-tested program contains malicious behavior is disclosed. The method includes steps of providing an emulator having a kernel and a plurality of installed hook points, wherein the kernel has a plurality of in-kernel functions; executing the to-be-tested program in the emulator dynamically to invoke the plurality of installed hook points to obtain a specific in-kernel function set from the plurality of in-kernel functions; and determining whether the to-be-tested program contains instructions for malicious behavior based on an invocation sequence of the specific in-kernel function set.Type: GrantFiled: October 11, 2014Date of Patent: August 29, 2017Assignee: NATIONAL CHIAO TUNG UNIVERSITYInventors: Chi-wei Wang, Chong-kuan Chen, Chia-wei Wang, Shiuhpyng Shieh
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Publication number: 20170083291Abstract: An automatic probe construction system and the method thereof are provided. The automatic probe construction system includes a data dereference analysis module, a probe selection module, and a probe verification module. The data dereference analysis module dereferences a plurality of target data of an electronic apparatus according to a plurality of pointers, and constructs a plurality of candidate probes. The probe selection module constructs a control flow graph according to the candidate probes and an instruction code of an executable image file, to select via the control flow graph from the candidate probes at least one dedicated probe. The probe verification module searches the executable image file for an instruction code corresponding to the dedicated probe, to verify the dedicated probe. Therefore, the dedicated probe can be constructed automatically, and the number of the dedicated probes is thus limited.Type: ApplicationFiled: February 4, 2016Publication date: March 23, 2017Inventors: Shiuhpyng Shieh, Chi-Wei Wang, Chia-Wei Wang, Chia-Wei Hsu
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Patent number: 9304792Abstract: A computer system and a method for tracking information flow are provided. The computer system divides an information flow tracking task into two decoupled tasks executed by two procedures. The first procedure emulates execution of instructions and divides the instructions into code blocks according to an instruction executing sequence. The first procedure translates the instructions of the code blocks into information flow codes and transmits them to the second procedure. The first procedure further translates the instructions into dynamic emulation instructions and executes the dynamic emulation instructions to generate addressing results of the dynamic addressing instructions. The second procedure executes the information flow codes according to the addressing results to emulate the instructions of the code blocks. Moreover, the method also tries to reduce the amount of data transmission between the two procedures when the first procedure executes the emulation task.Type: GrantFiled: April 30, 2012Date of Patent: April 5, 2016Assignee: National Chiao Tung UniversityInventors: Chi-Wei Wang, Shiuh-Pyng Shieh, Yen-Ju Liu
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Publication number: 20150242626Abstract: A method for determining whether a to-be-tested program contains malicious behavior is disclosed. The method includes steps of providing an emulator having a kernel and a plurality of installed hook points, wherein the kernel has a plurality of in-kernel functions; executing the to-be-tested program in the emulator dynamically to invoke the plurality of installed hook points to obtain a specific in-kernel function set from the plurality of in-kernel functions; and determining whether the to-be-tested program contains instructions for malicious behavior based on an invocation sequence of the specific in-kernel function set.Type: ApplicationFiled: October 11, 2014Publication date: August 27, 2015Inventors: Chi-wei Wang, Chong-kuan Chen, Chia-wei Wang, Shiuhpyng Shieh
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Patent number: 8970998Abstract: The present invention relates to compound semiconductor ESD protection devices of three types. The device comprises a multi-gate enhancement mode PET (E-PET). For the type I compound semiconductor ESD protection device, the source electrode is connected to the plural gate electrodes through at least one first resistor, and the drain electrode is connected to the plural gate electrodes through at least one second resistor. For the type II compound semiconductor ESD protection device, at least one of the plural gate electrodes are connected to at least one of the inter-gate regions between two adjacent gate electrodes through at least one fourth resistor. For the type compound semiconductor ESD protection device, the plural gate electrodes are connected to the source or drain electrodes through at least one seventh resistor. Any two gate electrodes in the three types of compound semiconductor ESD protection devices can be connected by a resistor.Type: GrantFiled: December 31, 2012Date of Patent: March 3, 2015Assignee: WIN Semiconductors Corp.Inventors: Shinichiro Takatani, Jung-Tao Chung, Chi-Wei Wang, Cheng-Guan Yuan, Shih-Ming Joseph Liu
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Patent number: 8964342Abstract: The present invention relates to compound semiconductor ESD protection devices using plural compound semiconductor E-FETs or compound semiconductor multi-gate E-FETs. The device comprises plural compound semiconductor E-FETs or multi-gate E-FETs, in which each of the gates is DC-connected to the source, drain, or an inter-gate region between two adjacent gates in the multi-gate E-FET through at least one first resistor, and at least one of the gates is AC-connected to the source, drain, or an inter-gate region between two adjacent gates in the multi-gate E-FET through a gate capacitor.Type: GrantFiled: December 31, 2012Date of Patent: February 24, 2015Assignee: WIN Semiconductors Corp.Inventors: Shinichiro Takatani, Jung-Tao Chung, Chi-Wei Wang, Cheng-Guan Yuan, Shih-Ming Joseph Liu
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Publication number: 20140183609Abstract: The present invention relates to compound semiconductor ESD protection devices using plural compound semiconductor E-FETs or compound semiconductor multi-gate E-FETs. The device comprises plural compound semiconductor E-FETs or multi-gate E-FETs, in which each of the gates is DC-connected to the source, drain, or an inter-gate region between two adjacent gates in the multi-gate E-FET through at least one first resister, and at least one of the gates is AC-connected to the source, drain, or an inter-gate region between two adjacent gates in the multi-gate E-FET through a gate capacitor.Type: ApplicationFiled: December 31, 2012Publication date: July 3, 2014Applicant: WIN Semiconductors Corp.Inventors: Shinichiro TAKATANI, Jung-Tao CHUNG, Chi-Wei WANG, Cheng-Guan YUAN, Shih-Ming Joseph LIU
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Publication number: 20140183544Abstract: The present invention relates to compound semiconductor ESD protection devices of three types. The device comprises a multi-gate enhancement mode FET (E-FET). For the type I compound semiconductor ESD protection device, the source electrode is connected to the plural gate electrodes through at least one first resistor, and the drain electrode is connected to the plural gate electrodes through at least one second resistor. For the type II compound semiconductor ESD protection device, the plural gate electrodes are connected to at least one of the inter-gate regions between two adjacent gate electrodes through at least one fourth resistor. For the type III compound semiconductor ESD protection device, the plural gate electrodes are connected to the source or drain electrodes through at least one seventh resistor. Any two gate electrodes in the three types of compound semiconductor ESD protection devices can be connected by a resistor.Type: ApplicationFiled: December 31, 2012Publication date: July 3, 2014Applicant: WIN Semiconductors Corp.Inventors: Shinichiro TAKATANI, Jung-Tao CHUNG, Chi-Wei WANG, Cheng-Guan YUAN, Shih-Ming Joseph LIU
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Publication number: 20140090076Abstract: A tracing device for detecting whether a specific attribute datum has a possibility of being stolen is provided. The tracing device includes a label map and a first processing device, wherein the label map has a specific label attached on the specific attribute datum and a buffer region, and the first processing device is coupled to the label map and determines whether there is the specific label in the buffer region.Type: ApplicationFiled: August 30, 2013Publication date: March 27, 2014Applicant: National Chiao Tung UniversityInventors: Chi-Wei Wang, Shiuhpyng Shieh, Chia-Huei Chang
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Patent number: 8595504Abstract: A method for authenticating a message in a network is provided. The method includes a step of generating, in a sink device, a private key and a public key. The private key includes a plurality of sub-private keys. The method further includes a step of generating, in the sink device, a signature for the message. The signature includes a sub-private key and an authentication path associated with the sub-private key in a hash tree. The hash tree is constructed during the generation of the sub-public keys.Type: GrantFiled: August 12, 2008Date of Patent: November 26, 2013Assignee: Industrial Technology Research InstituteInventors: Shih-I Huang, Shiuh-Pyng Shieh, Sheng-Ming Chang, Chi-Wei Wang
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Patent number: 8572643Abstract: In one embodiment of the present invention, a system for dynamic content distribution and grouping includes a server for providing a plurality of content channels, at least one tuning/decoding means for receiving/decoding at least one of the plurality of content channels, and at least one respective display means for displaying the at least one received/decoded content channel. In such embodiments of the present invention, the server is configured to dynamically configure the at least one tuning/decoding means to receive/decode at least one of the plurality of content channels. More specifically, in embodiments of the present invention, the server dynamically configures the at least one tuning/decoding means by communicating a channel change command to the at least one tuning/decoding means over a dedicated radio-frequency channel or, in an alternate embodiment, using an internet protocol.Type: GrantFiled: January 31, 2007Date of Patent: October 29, 2013Assignee: Thomson LicensingInventors: Gregory Charles Herlein, David Chi-Wei Wang
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Publication number: 20130185523Abstract: A computer system and a method for tracking information flow are provided. The computer system divides an information flow tracking task into two decoupled tasks executed by two procedures. The first procedure emulates execution of instructions and divides the instructions into code blocks according to an instruction executing sequence. The first procedure translates the instructions of the code blocks into information flow codes and transmits them to the second procedure. The first procedure further translates the instructions into dynamic emulation instructions and executes the dynamic emulation instructions to generate addressing results of the dynamic addressing instructions. The second procedure executes the information flow codes according to the addressing results to emulate the instructions of the code blocks. Moreover, the method also tries to reduce the amount of data transmission between the two procedures when the first procedure executes the emulation task.Type: ApplicationFiled: April 30, 2012Publication date: July 18, 2013Applicant: NATIONAL CHIAO TUNG UNIVERSITYInventors: Chi-Wei Wang, Shiuh-Pyng Shieh, Yen-Ju Liu
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Publication number: 20100042842Abstract: A method for authenticating a message in a network is provided. The method includes a step of generating, in a sink device, a private key and a public key. The private key includes a plurality of sub-private keys. The method further includes a step of generating, in the sink device, a signature for the message. The signature includes a sub-private key and an authentication path associated with the sub-private key in a hash tree. The hash tree is constructed during the generation of the sub-public keys.Type: ApplicationFiled: August 12, 2008Publication date: February 18, 2010Inventors: Shih-I Huang, Shiuh-Pyng Shieh, Sheng-Ming Chang, Chi-Wei Wang