Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.

Abstract: A semiconductor device includes a substrate. The semiconductor device includes a dielectric layer disposed over a portion of the substrate. The semiconductor device includes a diffusion blocking layer disposed over the dielectric layer. The diffusion blocking layer and the dielectric layer have different material compositions. The semiconductor device includes a ferroelectric layer disposed over the diffusion blocking layer.

Abstract: An image adjustment method, applied to an image sensing system comprising an image sensor, comprising: (a) sensing a target image by the image sensor; (b) dividing the target image to a plurality of image regions; (c) acquiring location information of at least one first target feature in the image regions; (d) computing brightness information of each of the image regions; (e) generating adjustment curves according to the brightness information and according to required brightness values of each of the image regions; and (f) adjusting brightness values of the image regions according to the adjustment curves. The step (d) adjusts the brightness information according to the location information or the step (e) adjusts the adjustment curves according to the location information.

Abstract: Provided are a precursor solution, and a modified layer and a lithium-based battery prepared by using the same. The modified layer is formed on the negative electrode, the positive electrode and/or the separator of the lithium-based battery by using the precursor solution through photo-polymerization reaction or thermal curing. The lithium-based battery comprising the modified layer effectively promotes the charge and discharge capability, cycling life, and safety. The modified layer can be applied to a roll-to-roll process. The formation of lithium dendrites in the lithium-based battery comprising the modified layer is significantly suppressed or reduced during the charge-discharge cycles. The shuttle effect is effectively suppressed or reduced in lithium sulfur batteries and lithium iodine batteries. All the above effects are beneficial to increasing the product value of lithium ion batteries, lithium metal batteries, anode-free lithium batteries, lithium sulfur batteries, and lithium iodine batteries.

Abstract: A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.

Abstract: Semiconductor device structures with a gate structure having different profiles at different portions of the gate structure may include a fin structure on a substrate, a source/drain structure on the fin structure, and a gate structure over the fin structure and along a sidewall of the fin. The source/drain structure is proximate the gate structure. The gate structure has a top portion having a first sidewall profile and a bottom portion having a second sidewall profile different from the first sidewall profile.

Abstract: Disclosed herein are novel single-stranded anti-sense oligonucleotides (ASOs) capable of reducing the transcription of thioredoxin domain containing protein 5 (TXNDC5) mRNA. Also disclosed is use of the single-stranded ASOs as disclosed herein for manufacturing medicaments suitable for treating a disease associated with upregulation of TXNDC5. Accordingly, a pharmaceutical composition comprising the disclosed ASO molecules is provided; as well as a method of treating a subject suffering from TXNDC5-mediated disease via administering to the subject the disclosed single-stranded ASO molecules.

Abstract: Provided are a gate structure and a method of forming the same. The gate structure includes a gate dielectric layer, a metal layer, and a cluster layer. The metal layer is disposed over the gate dielectric layer. The cluster layer is sandwiched between the metal layer and the gate dielectric layer, wherein the cluster layer at least includes an amorphous silicon layer, an amorphous carbon layer, or an amorphous germanium layer. In addition, a semiconductor device including the gate structure is provided.

Abstract: A HDR tone mapping system includes several modules. A semantic segmentation module is used to extract semantic information from the input image. An image decomposition module is used to decompose the input image to a high-bit base layer and a detail layer. A statistics module is used to generate statistics of pixels of the input image according to the semantic information. A curve computation module is used to generate a tone curve from the statistics. A compression module is used to compress the high-bit base layer to a low-bit base layer according to the tone curve, the statistics and the semantic information. A detail adjustment module is used to tune the detail layer according to the semantic information and the statistics to generate an adjusted detail layer. An image reconstruction module is used to combine the adjusted detail layer and the low-bit base layer to generate an output image.

Abstract: An optical lens assembly includes, in order from an object side to an image side: a first lens with negative refractive power; a second lens with negative refractive power; a third lens with positive refractive power; a fourth lens with positive refractive power; a fifth lens with negative refractive power; a sixth lens with positive refractive power; wherein a distance from an object-side surface of the first lens to an image plane along an optical axis is TL, an incident angle of a chief ray on the image plane at a maximum view angle of the optical lens assembly is CRA, a focal length of the optical lens assembly is f, and the following condition is satisfied: 51.73°<TL*CRA/f<129.65°.

Abstract: A system allocates scratchpad memory (SPM) to heterogeneous devices for neural network computing. The system executes the operations of a global optimization manager. The global optimization manager receives compilation states from compilers, which compile corresponding subgraphs of a neural network model into corresponding subcommands that run on the heterogeneous devices. The global optimization manager unifies records of a same object across different ones of the compilation states, and allocates the SPM to the subgraphs according to the unified records of the compilation states.

Abstract: The present invention relates to a chip tray positioning device, which mainly comprises a frame body, a tray conveying module, a pulling module, a pushing module and a controller. The tray conveying module is disposed on the frame body, electrically connected to the controller and controlled to convey a chip tray from the start area to the end area. The pulling module and the pushing module are disposed on the frame body, electrically connected to the controller and controlled to cause the chip tray to be abutted against the end wall and the lateral wall of the frame body, thereby realizing the positioning of the chip tray and eliminating an error formed in the transfer process of the chip tray. In addition, the controller also controls the pushing module to knock the chip tray at a specific frequency so that the chip tray is vibrated.

Abstract: A system allocates scratchpad memory (SPM) to heterogeneous devices for neural network computing. The system executes the operations of a global optimization manager. The global optimization manager receives compilation states from compilers, which compile corresponding subgraphs of a neural network model into corresponding subcommands that run on the heterogeneous devices. The global optimization manager unifies records of a same object across different ones of the compilation states, and allocates the SPM to the subgraphs according to the unified records of the compilation states.

Abstract: The present invention relates to a chip tray positioning device, which mainly comprises a frame body, a tray conveying module, a pulling module, a pushing module and a controller. The tray conveying module is disposed on the frame body, electrically connected to the controller and controlled to convey a chip tray from the start area to the end area. The pulling module and the pushing module are disposed on the frame body, electrically connected to the controller and controlled to cause the chip tray to be abutted against the end wall and the lateral wall of the frame body, thereby realizing the positioning of the chip tray and eliminating an error formed in the transfer process of the chip tray. In addition, the controller also controls the pushing module to knock the chip tray at a specific frequency so that the chip tray is vibrated.

Abstract: An automatic probe construction system and the method thereof are provided. The automatic probe construction system includes a data dereference analysis module, a probe selection module, and a probe verification module. The data dereference analysis module dereferences a plurality of target data of an electronic apparatus according to a plurality of pointers, and constructs a plurality of candidate probes. The probe selection module constructs a control flow graph according to the candidate probes and an instruction code of an executable image file, to select via the control flow graph from the candidate probes at least one dedicated probe. The probe verification module searches the executable image file for an instruction code corresponding to the dedicated probe, to verify the dedicated probe. Therefore, the dedicated probe can be constructed automatically, and the number of the dedicated probes is thus limited.

Abstract: A method for determining whether a to-be-tested program contains malicious behavior is disclosed. The method includes steps of providing an emulator having a kernel and a plurality of installed hook points, wherein the kernel has a plurality of in-kernel functions; executing the to-be-tested program in the emulator dynamically to invoke the plurality of installed hook points to obtain a specific in-kernel function set from the plurality of in-kernel functions; and determining whether the to-be-tested program contains instructions for malicious behavior based on an invocation sequence of the specific in-kernel function set.

Abstract: An automatic probe construction system and the method thereof are provided. The automatic probe construction system includes a data dereference analysis module, a probe selection module, and a probe verification module. The data dereference analysis module dereferences a plurality of target data of an electronic apparatus according to a plurality of pointers, and constructs a plurality of candidate probes. The probe selection module constructs a control flow graph according to the candidate probes and an instruction code of an executable image file, to select via the control flow graph from the candidate probes at least one dedicated probe. The probe verification module searches the executable image file for an instruction code corresponding to the dedicated probe, to verify the dedicated probe. Therefore, the dedicated probe can be constructed automatically, and the number of the dedicated probes is thus limited.

Abstract: A computer system and a method for tracking information flow are provided. The computer system divides an information flow tracking task into two decoupled tasks executed by two procedures. The first procedure emulates execution of instructions and divides the instructions into code blocks according to an instruction executing sequence. The first procedure translates the instructions of the code blocks into information flow codes and transmits them to the second procedure. The first procedure further translates the instructions into dynamic emulation instructions and executes the dynamic emulation instructions to generate addressing results of the dynamic addressing instructions. The second procedure executes the information flow codes according to the addressing results to emulate the instructions of the code blocks. Moreover, the method also tries to reduce the amount of data transmission between the two procedures when the first procedure executes the emulation task.

Abstract: A method for determining whether a to-be-tested program contains malicious behavior is disclosed. The method includes steps of providing an emulator having a kernel and a plurality of installed hook points, wherein the kernel has a plurality of in-kernel functions; executing the to-be-tested program in the emulator dynamically to invoke the plurality of installed hook points to obtain a specific in-kernel function set from the plurality of in-kernel functions; and determining whether the to-be-tested program contains instructions for malicious behavior based on an invocation sequence of the specific in-kernel function set.

Abstract: The present invention relates to compound semiconductor ESD protection devices of three types. The device comprises a multi-gate enhancement mode PET (E-PET). For the type I compound semiconductor ESD protection device, the source electrode is connected to the plural gate electrodes through at least one first resistor, and the drain electrode is connected to the plural gate electrodes through at least one second resistor. For the type II compound semiconductor ESD protection device, at least one of the plural gate electrodes are connected to at least one of the inter-gate regions between two adjacent gate electrodes through at least one fourth resistor. For the type compound semiconductor ESD protection device, the plural gate electrodes are connected to the source or drain electrodes through at least one seventh resistor. Any two gate electrodes in the three types of compound semiconductor ESD protection devices can be connected by a resistor.