Patents by Inventor Chi-Wen Liu

Chi-Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9893061
    Abstract: A multiple-fin device includes a substrate and a plurality of fins formed on the substrate. Source and drain regions are formed in the respective fins. A dielectric layer is formed on the substrate. The dielectric layer has a first thickness adjacent one side of a first fin and having a second thickness, different from the first thickness, adjacent an opposite side of the fin. A continuous gate structure is formed overlying the plurality of fins, the continuous gate structure being adjacent a top surface of each fin and at least one sidewall surface of at least one fin. By adjusting the dielectric layer thickness, channel width of the resulting device can be fine-tuned.
    Type: Grant
    Filed: April 11, 2016
    Date of Patent: February 13, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Patent number: 9893163
    Abstract: A 3D capacitor and method for fabricating a 3D capacitor is disclosed. An exemplary 3D capacitor includes a substrate including a fin structure, the fin structure including a plurality of fins. The 3D capacitor further includes an insulation material disposed on the substrate and between each of the plurality of fins. The 3D capacitor further includes a dielectric layer disposed on each of the plurality of fins. The 3D capacitor further includes a first electrode disposed on a first portion of the fin structure. The first electrode being in direct contact with a surface of the fin structure. The 3D capacitor further includes a second electrode disposed on a second portion of the fin structure. The second electrode being disposed directly on the dielectric layer and the first and second portions of the fin structure being different.
    Type: Grant
    Filed: November 4, 2011
    Date of Patent: February 13, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Publication number: 20180040720
    Abstract: A method comprises removing a portion of a fin to form a trench over a lower portion of the fin, wherein the lower portion is formed of a first semiconductor material, growing a second semiconductor material in the trench to form a middle portion of the fin, forming a first carbon doped layer over the middle portion of the fin, growing the first semiconductor material over the first carbon doped layer to form an upper portion of the fin, replacing outer portions of the upper portion of the fin with a second carbon doped layer and drain/source regions, wherein the first carbon doped layer and the second carbon doped layer are separated by the upper portion of the fin and applying a thermal oxidation process to the middle portion of the fin to form an oxide outer layer.
    Type: Application
    Filed: October 17, 2017
    Publication date: February 8, 2018
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen, Chao-Hsiung Wang, Chi-Wen Liu
  • Publication number: 20180040738
    Abstract: A device includes isolation regions extending into a semiconductor substrate, with a substrate strip between opposite portions of the isolation regions having a first width. A source/drain region has a portion overlapping the substrate strip, wherein an upper portion of the source/drain region has a second width greater than the first width. The upper portion of the source/drain region has substantially vertical sidewalls. A source/drain silicide region has inner sidewalls contacting the vertical sidewalls of the source/drain region.
    Type: Application
    Filed: October 19, 2017
    Publication date: February 8, 2018
    Inventors: Kuo-Cheng Ching, Ching-Wei Tsai, Chi-Wen Liu, Chih-Hao Wang, Ying-Keung Leung
  • Patent number: 9887137
    Abstract: In accordance with some embodiments, a device includes first and second p-type transistors. The first transistor includes a first channel region including a first material of a first fin. The first transistor includes first and second epitaxial source/drain regions each in a respective first recess in the first material and on opposite sides of the first channel region. The first transistor includes a first gate stack on the first channel region. The second transistor includes a second channel region including a second material of a second fin. The second material is a different material from the first material. The second transistor includes third and fourth epitaxial source/drain regions each in a respective second recess in the second material and on opposite sides of the second channel region. The second transistor includes a second gate stack on the second channel region.
    Type: Grant
    Filed: September 19, 2016
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Chi-Wen Liu
  • Patent number: 9887274
    Abstract: A FinFET and methods for forming a FinFET are disclosed. A method includes forming trenches in a semiconductor substrate to form a fin, depositing an insulating material within the trenches, and removing a portion of the insulating material to expose sidewalls of the fin. The method also includes recessing a portion of the exposed sidewalls of the fin to form multiple recessed surfaces on the exposed sidewalls of the fin, wherein adjacent recessed surfaces of the multiple recessed surfaces are separated by a lattice shift. The method also includes depositing a gate dielectric on the recessed portion of the sidewalls of the fin and depositing a gate electrode on the gate dielectric.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: February 6, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chun-Hsiang Fan, Tsu-Hsiu Perng, Chi-Kang Liu, Yung-Ta Li, Ming-Huan Tsai, Clement Hsingjen Wann, Chi-Wen Liu
  • Publication number: 20180026038
    Abstract: A method includes forming a first semiconductor strip on a substrate, the first semiconductor strip including a first crystalline semiconductor material on a substrate and a second crystalline semiconductor material above the first crystalline semiconductor material. A first portion of the first crystalline semiconductor material in first semiconductor strip is converted to a dielectric material, where a second portion of the first crystalline semiconductor material remains unconverted. Gate structures are formed over the first semiconductor strip and source/drain regions are formed on opposing sides of the gate structures.
    Type: Application
    Filed: August 14, 2017
    Publication date: January 25, 2018
    Inventors: Kuo-Cheng Ching, Chi-Wen Liu, Chih-Hao Wang
  • Patent number: 9876108
    Abstract: A method includes forming a gate stack on a middle portion of s semiconductor fin, and forming a first gate spacer on a sidewall of the gate stack. After the first gate spacer is formed, a template dielectric region is formed to cover the semiconductor fin. The method further includes recessing the template dielectric region. After the recessing, a second gate spacer is formed on the sidewall of the gate stack. The end portion of the semiconductor fin is etched to form a recess in the template dielectric region. A source/drain region is epitaxially grown in the recess.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: January 23, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Chi-Wen Liu, Ying-Keung Leung
  • Publication number: 20180019326
    Abstract: In a method of fabricating a field effect transistor, a fin structure made of a first semiconductor material is formed so that the fin structure protrudes from an isolation insulating layer disposed over a substrate. A gate structure is formed over a part of the fin structure, thereby defining a channel region, a source region and a drain region in the fin structure. After the gate structure is formed, laser annealing is performed on the fin structure.
    Type: Application
    Filed: July 14, 2016
    Publication date: January 18, 2018
    Inventors: Fang-Liang LU, CheeWee LIU, Chi-Wen LIU, Shih-Hsien HUANG, I-Hsieh WONG
  • Publication number: 20180012962
    Abstract: Exemplary FET devices having 2D material layer active regions and methods of fabricating thereof are described. For example, a black phosphorus active region has a first thickness in the channel region and a second, greater, thickness in the source/drain (S/D) region. The BP in the S/D region has a sidewall that interfaces a contact disposed over the FET. A gate electrode is disposed over the channel region. In some embodiments, the sidewall has passivated edge. In some embodiments, the sidewall is nonlinear. In some embodiments, the stress layer is disposed over the 2D material layer.
    Type: Application
    Filed: July 6, 2016
    Publication date: January 11, 2018
    Inventors: Ling-Yen Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Publication number: 20180012977
    Abstract: A representative fin field effect transistor (FinFET) includes a substrate having a major surface; a fin structure protruding from the major surface having a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material. A bottom portion of the upper portion comprises a dopant with a first peak concentration. A middle portion is disposed between the lower portion and upper portion, where the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant. An isolation structure surrounds the fin structure, where a portion of the isolation structure adjacent to the bottom portion of the upper portion comprises the dopant with a second peak concentration equal to or greater than the first peak concentration.
    Type: Application
    Filed: September 7, 2017
    Publication date: January 11, 2018
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen, Chao-Hsiung Wang, Chi-Wen Liu
  • Publication number: 20180013012
    Abstract: In a method for manufacturing a metallic-channel device, a metallic layer is formed on a substrate. The metallic layer is formed by an atomic layer deposition technique and has a first thickness. An insulating layer is formed over the metallic layer. A gate contact layer is formed over the insulating layer. The formed layers are processed to remove the gate contact layer, the insulating layer, and a portion of the metallic layer from a source-drain region. A remaining portion of the metallic layer on the source-drain region has a second thickness that is smaller than the first thickness. Source and drain metal contacts are formed over the remaining portion of the metallic layer.
    Type: Application
    Filed: July 8, 2016
    Publication date: January 11, 2018
    Inventors: Miin-Jang CHEN, Chi-Wen LIU, Po-Hsien CHENG
  • Publication number: 20180005824
    Abstract: In a method of fabricating a field effect transistor, a Mo layer is formed on the substrate. The Mo layer is sulfurized to convert it into a MoS2 layer. Source and drain electrodes are formed on the MoS2 layer. The MoS2 layer is treated with low-power oxygen plasma. A gate dielectric layer is formed on the MoS2 layer. A gate electrode is formed on the gate dielectric layer. An input electric power in the low-power oxygen plasma treatment is in a range from 15 W to 50 W.
    Type: Application
    Filed: June 29, 2016
    Publication date: January 4, 2018
    Inventors: Shih-Yen LIN, Chi-Wen LIU, Si-Chen LEE, Chong-Rong WU, Kuan-Chao CHEN
  • Patent number: 9859380
    Abstract: A device includes a substrate and insulation regions over a portion of the substrate. A first semiconductor region is between the insulation regions and having a first conduction band. A second semiconductor region is over and adjoining the first semiconductor region, wherein the second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin. The second semiconductor region also includes a wide portion and a narrow portion over the wide portion, wherein the narrow portion is narrower than the wide portion. The semiconductor fin has a tensile strain and has a second conduction band lower than the first conduction band. A third semiconductor region is over and adjoining a top surface and sidewalls of the semiconductor fin, wherein the third semiconductor region has a third conduction band higher than the second conduction band.
    Type: Grant
    Filed: March 6, 2017
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Jing Lee, Chi-Wen Liu, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann
  • Patent number: 9859429
    Abstract: An integrated circuit structure includes a semiconductor substrate, and isolation regions extending into the semiconductor substrate, wherein the isolation regions have opposite sidewalls facing each other. A fin structure includes a silicon fin higher than top surfaces of the isolation regions, a germanium-containing semiconductor region overlapped by the silicon fin, silicon oxide regions on opposite sides of the germanium-containing semiconductor region, and a germanium-containing semiconductor layer between and in contact with the silicon fin and one of the silicon oxide regions.
    Type: Grant
    Filed: September 3, 2013
    Date of Patent: January 2, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Jiun-Jia Huang, Chao-Hsiung Wang, Chi-Wen Liu
  • Publication number: 20170373190
    Abstract: A device includes a substrate, insulation regions extending into the substrate, a first semiconductor region between the insulation regions and having a first valence band, and a second semiconductor region over and adjoining the first semiconductor region. The second semiconductor region has a compressive strain and a second valence band higher than the first valence band. The second semiconductor region includes an upper portion higher than top surfaces of the insulation regions to form a semiconductor fin, and a lower portion lower than the top surfaces of the insulation regions. The upper portion and the lower portion are intrinsic. A semiconductor cap adjoins a top surface and sidewalls of the semiconductor fin. The semiconductor cap has a third valence band lower than the second valence band.
    Type: Application
    Filed: August 28, 2017
    Publication date: December 28, 2017
    Inventors: Yi-Jing Lee, Chi-Wen Liu
  • Patent number: 9853101
    Abstract: Transistor structures and methods of forming transistor structures are provided. The transistor structures include alternating layers of a first epitaxial material and a second epitaxial material. In some embodiments, one of the first epitaxial material and the second epitaxial material may be removed for one of an n-type or p-type transistor. A bottommost layer of the first epitaxial material and the second epitaxial material maybe be removed, and sidewalls of one of the first epitaxial material and the second epitaxial material may be indented or recessed.
    Type: Grant
    Filed: November 6, 2015
    Date of Patent: December 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yi Peng, Hung-Li Chiang, Yu-Lin Yang, Chih Chieh Yeh, Yee-Chia Yeo, Chi-Wen Liu
  • Patent number: 9853125
    Abstract: A tunneling field-effect transistor (TFET) device is disclosed. A frustoconical protrusion structure is disposed over the substrate and protrudes out of the plane of substrate. A drain region is disposed over the substrate adjacent to the frustoconical protrusion structure and extends to a bottom portion of the frustoconical protrusion structure as a raised drain region. A gate stack is disposed over the substrate. The gate stack has a planar portion, which is parallel to the surface of substrate and a gating surface, which wraps around a middle portion of the frustoconical protrusion structure, including overlapping with the raised drain region. An isolation dielectric layer is disposed between the planar portion of the gate stack and the drain region. A source region is disposed as a top portion of the frustoconical protrusion structure, including overlapping with a top portion of the gating surface of the gate stack.
    Type: Grant
    Filed: November 10, 2015
    Date of Patent: December 26, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Harry-Hak-Lay Chuang, Cheng-Cheng Kuo, Chi-Wen Liu, Ming Zhu
  • Publication number: 20170365719
    Abstract: A gate structure of a negative capacitance field effect transistor (NCFET) is disclosed. The NCFET includes a gate stack disposed over a substrate. The gate stack includes a dielectric material layer, a ferroelectric ZrO2 layer and a first conductive layer. The NCFET also includes a source/drain feature disposed in the substrate adjacent the gate stack.
    Type: Application
    Filed: June 15, 2016
    Publication date: December 21, 2017
    Inventors: Miin-Jang Chen, Chi-Wen Liu, Bo-Ting Lin
  • Publication number: 20170365674
    Abstract: A semiconductor device and a method of forming the semiconductor device is disclosed. A sacrificial film is used to pattern a contact to a semiconductor structure, such as a contact to a source/drain region of a transistor. The contact may include a tapered profile along an axis parallel to the gate electrode such that an outermost width of the contact decreases as the contact extends away from the source/drain region.
    Type: Application
    Filed: December 1, 2016
    Publication date: December 21, 2017
    Inventors: Tung Ying Lee, Chih Chieh Yeh, Jeng-Ya David Yeh, Yuan-Hung Chiu, Chi-Wen Liu, Yee-Chia Yeo