Patents by Inventor Chi-Wen Liu

Chi-Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Interconnection Structure, Fabricating Method Thereof, and Semiconductor Device Using the Same
    Publication number: 20170358531
    Abstract: A semiconductor device includes a semiconductor substrate comprising a contact region, a silicide present on the contact region, a dielectric layer present on the semiconductor substrate, the dielectric layer comprising an opening to expose a portion of the contact region, a conductor present in the opening, a barrier layer present between the conductor and the dielectric layer, and a metal layer present between the barrier layer and the dielectric layer, wherein a Si concentration of the silicide is varied along a height of the silicide.
    Type: Application
    Filed: July 31, 2017
    Publication date: December 14, 2017
    Inventors: Yu-Hung Lin, Chi-Wen Liu, Horng-Huei Tseng
  • Semiconductor device and formation thereof
    Patent number: 9837537
    Abstract: A semiconductor device and method of formation are provided herein. A semiconductor device includes a barrier including carbon over a fin, the fin including a doped region. The semiconductor device includes an epitaxial (Epi) cap over the barrier, the Epi cap including phosphorus. The barrier inhibits phosphorus diffusion from the Epi cap into the fin as compared to a device that lacks such a barrier. The inhibition of the phosphorus diffusion reduces a short channel effect, thus improving the semiconductor device function.
    Type: Grant
    Filed: February 17, 2014
    Date of Patent: December 5, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen, Chao-Hsiung Wang, Chi-Wen Liu
  • Semiconductor device and manufacturing method thereof
    Patent number: 9837538
    Abstract: A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin structure includes a bulk stressor layer formed on the substrate layer and a channel layer disposed over the bulk stressor layer. An oxide layer is formed on the substrate layer extending away from the channel layer. A source-drain (SD) stressor structure is disposed on sidewalls of the channel layer over the oxide layer. A gate stack including a gate electrode layer and a gate dielectric layer covers a portion of the channel layer and extends in a second direction perpendicular to the first direction.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: December 5, 2017
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL CHIAO TUNG UNIVERSITY
    Inventors: Chao-Hsin Chien, Chi-Wen Liu, Chen-Han Chou
  • Semiconductor Device with Transition Metal Dichalocogenide Hetero-Structure
    Publication number: 20170345944
    Abstract: The present disclosure provides a semiconductor device in accordance with some embodiments. The semiconductor device includes a first transition metal dichalcogenide film on a substrate; a second transition metal dichalcogenide film on the first transition metal dichalcogenide film; source and drain features formed over the second transition metal dichalcogenide film; and a first gate stack formed over the second transition metal dichalcogenide film and interposed between the source and drain feature.
    Type: Application
    Filed: May 31, 2016
    Publication date: November 30, 2017
    Inventors: Shih-Yen Lin, Chi-Wen Liu, Chong-Rong Wu, Xian-Rui Chang
  • Semiconductor Device and Manufacturing Method Thereof
    Publication number: 20170330959
    Abstract: A semiconductor device includes a substrate, at least one active semiconductor fin, at least one first dummy semiconductor fin, and at least one second dummy semiconductor fin. The active semiconductor fin is disposed on the substrate. The first dummy semiconductor fin is disposed on the substrate. The second dummy semiconductor fin is disposed on the substrate and between the active semiconductor fin and the first dummy semiconductor fin. A top surface of the first dummy semiconductor fin and a top surface of the second dummy semiconductor fin are curved in different directions.
    Type: Application
    Filed: July 31, 2017
    Publication date: November 16, 2017
    Inventors: Chih-Sheng Li, Hsin-Chieh Huang, Chi-Wen Liu
  • FETs and methods for forming the same
    Patent number: 9818878
    Abstract: FETs and methods for forming FETs are disclosed. A structure comprises a substrate, a gate dielectric and a gate electrode. The substrate comprises a fin, and the fin comprises an epitaxial channel region. The epitaxial channel has a major surface portion of an exterior surface. The major surface portion comprising at least one lattice shift, and the at least one lattice shift comprises an inward or outward shift relative to a center of the fin. The gate dielectric is on the major surface portion of the exterior surface. The gate electrode is on the gate dielectric.
    Type: Grant
    Filed: May 11, 2016
    Date of Patent: November 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yu-Lien Huang, Chun-Hsiang Fan, Tung Ying Lee, Chi-Wen Liu
  • Integrated Circuit Structure and Method with Solid Phase Diffusion
    Publication number: 20170323943
    Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a fin active region formed on a semiconductor substrate and spanning between a first sidewall of a first shallow trench isolation (STI) feature and a second sidewall of a second STI feature; an anti-punch through (APT) feature of a first type conductivity; and a channel material layer of the first type conductivity, disposed on the APT feature and having a second doping concentration less than the first doping concentration.
    Type: Application
    Filed: July 24, 2017
    Publication date: November 9, 2017
    Inventors: Cheng-Yi Peng, Ling-Yen Yeh, Chi-Wen Liu, Chih-Sheng Chang, Yee-Chia Yeo
  • Methods of forming an interconnect structure using a self-ending anodic oxidation
    Patent number: 9812395
    Abstract: A method of forming low-k interconnect structure is disclosed, which comprises: providing at least one protruding structure on a substrate traversing between a first connection region to a second connection region defined thereon; performing anodic oxidation on the substrate having the protruding structure; forming one or more nanowire interconnect in the protruding structure traversing between the first connection region and the second connection region; the nanowire interconnect being surrounded by a dielectric layer formed during the anodic oxidation.
    Type: Grant
    Filed: October 7, 2014
    Date of Patent: November 7, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company Limited & National Taiwan University
    Inventors: Jenn-Gwo Hwu, Wei-Cheng Tian, Samuel C. Pan, Chao-Hsiung Wang, Chi-Wen Liu
  • High-K Dielectric and Method of Manufacture
    Publication number: 20170317182
    Abstract: A semiconductor device and method of manufacturing same are described. A first hafnium oxide (HfO2) layer is formed on a substrate. A titanium (Ti) layer is formed over the first hafnium oxide layer. A second hafnium oxide layer is formed over the titanium layer. The composite device structure is thermally annealed to produce a high-k dielectric structure having a hafnium titanium oxide (HfxTi1-xO2) layer interposed between the first hafnium oxide layer and the second hafnium oxide layer.
    Type: Application
    Filed: September 1, 2016
    Publication date: November 2, 2017
    Inventors: I-Chen Huang, Yi-Ju Hsu, Chi-Wen Liu, Kuang-Hsin Chen, Yung-Hsien Wu, Chin-Yu Chen
  • ONE-DIMENSIONAL NANOSTRUCTURE GROWTH ON GRAPHENE AND DEVICES THEREOF
    Publication number: 20170317181
    Abstract: A method and structure for providing a GAA device. In some embodiments, a substrate including an insulating layer disposed thereon is provided. By way of example, a first metal portion is formed within the insulating layer. In various embodiments, a first lateral surface of the first metal portion is exposed. After exposure of the first lateral surface of the first metal portion, a first graphene layer is formed on the exposed first lateral surface. In some embodiments, the first graphene layer defines a first vertical plane parallel to the exposed first lateral surface. Thereafter, in some embodiments, a first nanobar is formed on the first graphene layer, where the first nanobar extends in a first direction normal to the first vertical plane defined by the first graphene layer.
    Type: Application
    Filed: July 17, 2017
    Publication date: November 2, 2017
    Inventors: Che-Wei YANG, Chi-Wen LIU, Hao-Hsiung LIN, Ling-Yen YEH
  • FinFET structure and method for fabricating the same
    Patent number: 9806178
    Abstract: A method comprises recessing a substrate to form a fin enclosed by an isolation region, wherein the substrate is formed of a first semiconductor material, recessing the fin to form a trench over a lower portion of the fin, growing a second semiconductor material in the trench to form a middle portion of the fin through a first epitaxial process, forming a first carbon doped layer over the lower portion through a second epitaxial process, growing the first semiconductor material over the first carbon doped layer to form an upper portion of the fin through a third epitaxial process, forming a first source/drain region through a fourth epitaxial process, wherein a second carbon doped layer is formed underlying the first source/drain region and applying a thermal oxidation process to the middle portion of the fin to form an oxide outer layer.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: October 31, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen, Chao-Hsiung Wang, Chi-Wen Liu
  • FinFET device and method of manufacturing same
    Patent number: 9806076
    Abstract: A semiconductor device and method for fabricating a semiconductor device is disclosed. An exemplary semiconductor device includes a substrate including a fin structure disposed over the substrate. The fin structure includes one or more fins. The semiconductor device further includes an insulation material disposed on the substrate. The semiconductor device further includes a gate structure disposed on a portion of the fin structure and on a portion of the insulation material. The gate structure traverses each fin of the fin structure. The semiconductor device further includes a source and drain feature formed from a material having a continuous and uninterrupted surface area. The source and drain feature includes a surface in a plane that is in direct contact with a surface in a parallel plane of the insulation material, each of the one or more fins of the fin structure, and the gate structure.
    Type: Grant
    Filed: February 22, 2016
    Date of Patent: October 31, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chi-Wen Liu, Chao-Hsiung Wang
  • Metal gate of gate-all-around transistor
    Patent number: 9786774
    Abstract: The disclosure relates to a semiconductor device. An exemplary structure for a semiconductor device comprises a nanowire structure comprising a channel region between a source region and a drain region; and a metal gate surrounding a portion the channel region, wherein the metal gate comprising a first gate portion adjacent to the source region having a first thickness and a second gate portion adjacent to the drain region having a second thickness less than the first thickness.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: October 10, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jean-Pierre Colinge, Chi-Wen Liu
  • Passivated and Faceted for Fin Field Effect Transistor
    Publication number: 20170278971
    Abstract: A fin field effect transistor (FinFET), and a method of forming, is provided. The FinFET has a fin having one or more semiconductor layers epitaxially grown on a substrate. A first passivation layer is formed over the fins, and isolation regions are formed between the fins. An upper portion of the fins are reshaped and a second passivation layer is formed over the reshaped portion. Thereafter, a gate structure may be formed over the fins and source/drain regions may be formed.
    Type: Application
    Filed: June 12, 2017
    Publication date: September 28, 2017
    Inventors: Yen-Yu Chen, Chi-Yuan Shih, Chi-Wen Liu
  • SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THEREOF
    Publication number: 20170278968
    Abstract: A semiconductor device includes a fin extending along a first direction over a substrate, and a gate structure extending in a second direction overlying the fin. The gate structure includes a gate dielectric layer overlying the fin, a gate electrode overlying the gate dielectric layer, and insulating gate sidewalls on opposing lateral surfaces of the gate electrode extending along the second direction. A source/drain region is formed in the fin in a region adjacent the gate electrode structure, and a stressor layer is between the source/drain region and the semiconductor substrate. The stressor layer includes GeSn or SiGeSn containing 1019 atoms cm? or less of a dopant, and a portion of the fin under the gate structure is a channel region.
    Type: Application
    Filed: September 27, 2016
    Publication date: September 28, 2017
    Inventors: Huang-Siang LAN, CheeWee LIU, Chi-Wen LIU, Shih-Hsien HUANG, I-Hsieh WONG, Hung-Yu YEH, Chung-En TSAI
  • SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF
    Publication number: 20170278962
    Abstract: A semiconductor device including a Fin FET device includes a fin structure extending in a first direction and protruding from a substrate layer. The fin structure includes a bulk stressor layer formed on the substrate layer and a channel layer disposed over the bulk stressor layer. An oxide layer is formed on the substrate layer extending away from the channel layer. A source-drain (SD) stressor structure is disposed on sidewalls of the channel layer over the oxide layer. A gate stack including a gate electrode layer and a gate dielectric layer covers a portion of the channel layer and extends in a second direction perpendicular to the first direction.
    Type: Application
    Filed: July 20, 2016
    Publication date: September 28, 2017
    Inventors: Chao-Hsin CHIEN, Chi-Wen LIU, Chen-Han CHOU
  • Method for fabricating a fine structure
    Patent number: 9773662
    Abstract: In a method for fabricating a fine structure, a metal oxide layer is formed by using an atomic layer deposition over a substrate, and the metal oxide layer is removed. An interfacial oxide layer is formed between the metal oxide layer and the substrate. The interfacial oxide layer is an oxide of an element constituting the substrate, and the interfacial oxide layer is removed.
    Type: Grant
    Filed: June 3, 2016
    Date of Patent: September 26, 2017
    Assignees: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Miin-Jang Chen, Chi-Wen Liu, Po-Hsien Cheng
  • Isolation structure of fin field effect transistor
    Patent number: 9773892
    Abstract: A representative fin field effect transistor (FinFET) includes a substrate having a major surface; a fin structure protruding from the major surface having a lower portion comprising a first semiconductor material having a first lattice constant; an upper portion comprising the first semiconductor material. A bottom portion of the upper portion comprises a dopant with a first peak concentration. A middle portion is disposed between the lower portion and upper portion, where the middle portion comprises a second semiconductor material having a second lattice constant different from the first lattice constant. An isolation structure surrounds the fin structure, where a portion of the isolation structure adjacent to the bottom portion of the upper portion comprises the dopant with a second peak concentration equal to or greater than the first peak concentration.
    Type: Grant
    Filed: February 5, 2016
    Date of Patent: September 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Guan-Lin Chen, Chao-Hsiung Wang, Chi-Wen Liu
  • FETs and methods of forming FETs
    Patent number: 9773786
    Abstract: An embodiment is a method including forming a first fin and a second fin on a substrate, the first fin and the second fin each including a first crystalline semiconductor material on a substrate and a second crystalline semiconductor material above the first crystalline semiconductor material. Converting the first crystalline semiconductor material in the second fin to a dielectric material, wherein after the converting step, at least a portion of the first crystalline semiconductor material in the first fin remains unconverted. Forming gate structures over the first fin and the second fin, and forming source/drain regions on opposing sides of the gate structures.
    Type: Grant
    Filed: April 30, 2015
    Date of Patent: September 26, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Kuo-Cheng Ching, Chi-Wen Liu, Chih-Hao Wang
  • Method of Fabricating a Semiconductor Device Having Modified Profile Metal Gate
    Publication number: 20170271469
    Abstract: A method of forming a semiconductor device having a semiconductor substrate with a dielectric layer disposed thereon. A trench is defined in the dielectric layer. A metal gate structure is formed in the trench. The metal gate structure includes a first layer and a second layer disposed on the first layer. The first layer extends to a first height in the trench and the second layer extends to a second height in the trench; the second height is greater than the first height. In some embodiments, the second layer is a work function metal and the first layer is a dielectric. In some embodiments, the second layer is a barrier layer.
    Type: Application
    Filed: June 5, 2017
    Publication date: September 21, 2017
    Inventors: Yu-Lien Huang, Chi-Wen LIU, Clement Hsingjen WANN, Ming-Huan TSAI, Zhao-Cheng CHEN