Abstract: A sliding cover faceplate and an electronic device using the same are provided. The sliding cover faceplate includes a sliding cover, a cover plate, and a sliding structure. The cover plate is provided on the electronic device, and the sliding cover is disposed on one side of the cover plate. The sliding structure includes a guiding portion and an elastic positioning portion. The guiding portion is disposed on the cover plate and is connected to the sliding cover to guide the sliding cover to slide between a first location and a second location on the cover plate. The elastic positioning portion connects the cover plate with the sliding cover to provide an elastic force to the sliding cover, such that when the sliding cover slides close to the first location or the second location, the sliding cover is automatically positioned on the first location or the second location.

Abstract: A sliding cover faceplate and an electronic device using the same are provided. The sliding cover faceplate includes a sliding cover, a cover plate, and a sliding structure. The cover plate is provided on the electronic device, and the sliding cover is disposed on one side of the cover plate. The sliding structure includes a guiding portion and an elastic positioning portion. The guiding portion is disposed on the cover plate and is connected to the sliding cover to guide the sliding cover to slide between a first location and a second location on the cover plate. The elastic positioning portion connects the cover plate with the sliding cover to provide an elastic force to the sliding cover, such that when the sliding cover slides close to the first location or the second location, the sliding cover is automatically positioned on the first location or the second location.

Abstract: A method of stabilizing plating film impurities in an electrochemical plating bath solution is disclosed. The method includes providing an electrochemical plating machine in which an electrochemical plating process is carried out. A by-product bath solution is formed by continually removing a pre-filtered bath solution from the machine and removing an additive from the pre-filtered bath solution. A clean bath solution is formed by removing an additive by-product from the by-product bath solution. An additive bath solution is formed by adding a fresh additive to the clean bath solution. The additive bath solution is added to the electrochemical plating machine. An apparatus for stabilizing film impurities in an electrochemical plating bath solution is also disclosed.

Abstract: A method of creating a resist image on a semiconductor substrate includes exposing a layer of photoresist on the semiconductor substrate and developing the exposed layer of photoresist using a first fluid including supercritical carbon dioxide and a base such as Tetra-Methyl Ammonium Hydroxide (TMAH). Additionally, the developed photoresist can be cleaned using a second fluid including supercritical carbon dioxide and a solvent such as methanol, ethanol, isopropanol, and xylene.

Abstract: A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cm2 current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a H2 plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm2 current density and second deposition step at a 60 mA/cm2 current density is used to deposit a second copper layer that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.

Abstract: A portable device comprising: a main body; a display and a keypad formed on the main body; a MP3 or MP4 codec formed within the main body; a memory coupled to the MP3 or MP4 codec; an audio process coupled to the MP3 or MP4 codec; a D/A converter coupled to the audio process; a solar cell array attached to an outer surface of the main body so as to be exposed to an external environment for generating a voltage when light is received. The memory includes nonvolatile memory or hard disc.

Abstract: A sliding cover faceplate and an electronic device using the same are provided. The sliding cover faceplate includes a sliding cover, a cover plate, and a sliding structure. The cover plate is provided on the electronic device, and the sliding cover is disposed on one side of the cover plate. The sliding structure includes a guiding portion and an elastic positioning portion. The guiding portion is disposed on the cover plate and is connected to the sliding cover to guide the sliding cover to slide between a first location and a second location on the cover plate. The elastic positioning portion connects the cover plate with the sliding cover to provide an elastic force to the sliding cover, such that when the sliding cover slides close to the first location or the second location, the sliding cover is automatically positioned on the first location or the second location.

Abstract: An apparatus including a pillar located over a substrate and having at least one sloped surface oriented at an acute angle relative to the substrate. The apparatus also includes an MRAM stack substantially conforming to the sloped surface, the MRAM stack thereby also oriented at the acute angle relative to the substrate. The MRAM stack may comprise a plurality of substantially planar, parallel layers each oriented at an acute angle relative to the substrate.

Abstract: A method of forming a metal layer with reduced defects comprising providing a structure having a dielectric layer formed over it, forming a dielectric layer having an opening, lining the opening with a metal seed layer, treating the metal seed layer with a cleaning process to remove contaminates from it, and forming a metal layer upon the metal seed layer.

Abstract: A dual contact ring for contacting a patterned surface of a wafer and electrochemical plating of a metal on the patterned central region of the wafer and removing the metal from the outer, edge region of the wafer. The dual contact ring has an outer voltage ring in contact with the outer, edge region of the wafer and an inner voltage ring in contact with the inner, central region of the wafer. The outer voltage ring is connected to a positive voltage source and the inner voltage ring is connected to a negative voltage source. The inner voltage ring applies a negative voltage to the wafer to facilitate the plating of metal onto the patterned region of the wafer. A positive voltage is applied to the wafer through the outer voltage ring to remove the plated metal from the outer, edge region of the substrate.

Abstract: A magnetic memory includes two first magnetic layers each oriented over a substrate, a second magnetic layer interposing the two first magnetic layers, and two dielectric layers each contacting the second magnetic layer and interposing the second magnetic layer and one of the two first magnetic layers. Each of the first and second magnetic layers and the dielectric layers may be oriented substantially perpendicular to the substrate or at an acute angle relative to the substrate.

Abstract: A method of forming a metal-filled opening in a semiconductor or other submicron device substrate includes forming a conductive bulk layer over the substrate surface and in the opening, wherein the conductive bulk layer has a first grain size. A conductive cap layer is formed over the conductive bulk layer, the conductive cap layer having a second grain size that is substantially smaller than the first grain size. At least one of the conductive bulk and cap layers are then planarized to form a planar surface that is substantially coincident with the substrate surface.

Abstract: The disclosure relates to a method and apparatus for enhancing copper film quality with a two-step deposition. The two step deposition may include depositing a first copper film by electrochemical plating, annealing the first copper film at a desired temperature for a duration of time to remove any impurities, depositing a second copper film and annealing the second copper film for a duration of time to remove impurities. The second copper film can be deposited by electrochemical plating without HCl/C-based additive. The second copper film can also be deposited by sputtering to avoid impurities including C, Cl and S.

Abstract: A method of reducing the pattern effect in the CMP process. The method comprises the steps of providing a semiconductor substrate having a patterned dielectric layer, a barrier layer on the patterned dielectric layer, and a conductive layer on the barrier layer; performing a first CMP process to remove part of the conductive layer before the barrier layer is polished, thereby a step height of the conductive layer is reduced; depositing a layer of material substantially the same as the conductive layer on the conductive layer; and performing a second CMP process to expose the dielectric layer. A method of eliminating the dishing phenomena after a CMP process and a CMP rework method are also provided.

Abstract: The portable device comprises a control IC imbedded in the portable device and a RF module coupled to the control IC for wireless communication. A display and an input unit are coupled to said control IC. Memory is coupled to the control IC to store data and a projection display module is coupled to said control IC for the data projection. The projection display module includes three liquid crystal panels that perform image displays in red, green, and blue, respectively; light emitting sources employed and positioned in correspondence with the liquid crystal panels, respectively. A dichroic prism is used for each display color combination, wherein the liquid crystal panels and the said light emitting sources are positioned on the light-incidence side of the side surfaces of said dichroic prism. A projection lens is provided on the light emission side of the dichroic prism.

Abstract: A method of forming a protective layer over a metal filled semiconductor feature to prevent metal oxidation including providing a semiconductor process wafer comprising an insulating dielectric layer having an opening for forming a semiconductor feature; blanket depositing a metal layer over the opening to substantially fill the opening; and, blanket depositing a protective layer comprising at least one of a oxidation resistant metal and metal nitride over the metal layer.

Abstract: Two problems seen in CMP as currently executed are a tendency for slurry particles to remain on the surface and the formation of a final layer of oxide. These problems have been solved by adding to the slurry a quantity of TMAH or TBAH. This has the effect of rendering the surface being polished hydrophobic. In that state a residual layer of oxide will not be left on the surface at the conclusion of CMP. Nor will many slurry abrasive particles remain cling to the freshly polished surface. Those that do are readily removed by a simple rinse or buffing. As an alternative, the CMP process may be performed in three stages—first convention CMP, then polishing in a solution of TMAH or TBAH, and finally a gentle rinse or buffing.

Abstract: A novel method for preventing the formation of voids in metal interconnects fabricated on a wafer, particularly during a thermal anneal process, is disclosed. The method includes fabricating metal interconnects between metal lines on a wafer. During a thermal anneal process carried out to reduce electrical resistance of the interconnects, the wafer is positioned in spaced-apart relationship to a wafer heater. This spacing configuration facilitates enhanced stabilility and uniformity in heating of the wafer by reducing the presence of particles on and providing a uniform flow of heated air or gas against and the wafer backside. This eliminates or at least substantially reduces the formation of voids in the interconnects during the anneal process.

Abstract: A method of forming a copper interconnect in a dual damascene scheme is described. After a diffusion barrier layer and seed layer are sequentially formed on the sidewalls and bottoms of a trench and via in a dielectric layer, a first copper layer is deposited by a first ECP process at a 10 mA/cm2 current density to fill the via and part of the trench. A first anneal step is performed to remove carbon impurities and optionally includes a H2 plasma treatment. A second ECP process with a first deposition step at a 40 mA/cm2 current density and second deposition step at a 60 mA/cm2 current density is used to deposit a second copper layer that overfills the trench. After a second anneal step, a CMP process planarizes the copper layers. Fewer copper defects, reduced S, Cl, and C impurities, and improved Rc performance are achieved by this method.

Abstract: A method for forming a copper dual damascene with improved copper migration resistance and improved electrical resistivity including providing a semiconductor wafer including upper and lower dielectric insulating layers separated by a middle etch stop layer; forming a dual damascene opening extending through a thickness of the upper and lower dielectric insulating layers wherein an upper trench line portion extends through the upper dielectric insulating layer thickness and partially through the middle etch stop layer; blanket depositing a barrier layer including at least one of a refractory metal and refractory metal nitride to line the dual damascene opening; carrying out a remote plasma etch treatment of the dual damascene opening to remove a bottom portion of the barrier layer to reveal an underlying conductive area; and, filling the dual damascene opening with copper to provide a substantially planar surface.