Patents by Inventor Chi-Woo Kim

Chi-Woo Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7575963
    Abstract: First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300° C. for 5 minutes, and a semiconductor layer an ohmic contact layer are sequentially formed. Next, a conductor layer of a metal such as Cr is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad. Next, indium zinc oxide is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively connected to the drain electrode, the gate pad and the data pad.
    Type: Grant
    Filed: October 18, 2007
    Date of Patent: August 18, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyang-Shik Kong, Myung-Koo Hur, Chi-Woo Kim
  • Patent number: 7557050
    Abstract: In a method of manufacturing a polysilicon thin film and a method of manufacturing a TFT having the thin film, a laser beam is irradiated on a portion of an amorphous silicon thin film to liquefy the portion of the amorphous silicon thin film. The amorphous silicon thin film is on a first end portion of a substrate. The liquefied silicon is crystallized to form silicon grains. The laser beam is shifted from the first end portion towards a second end portion of the substrate opposite the first end portion by an interval in a first direction. The laser beam is then irradiated onto a portion of the amorphous silicon thin film adjacent to the silicon grains to form a first polysilicon thin film. Therefore, electrical characteristics of the amorphous silicon thin film may be improved.
    Type: Grant
    Filed: September 23, 2005
    Date of Patent: July 7, 2009
    Assignee: Samsung Electroncis Co., Ltd.
    Inventors: Se-Jin Chung, Chi-Woo Kim, Ui-Jin Chung, Dong-Byum Kim
  • Patent number: 7511793
    Abstract: In a liquid crystal display, a plurality of gate lines and data lines are provided on a first substrate including a display area as a screen, and a peripheral area external to the display area wherein a plurality of pixel electrodes are electrically connected to the gate lines and to the data lines, and some of the pixel electrodes extend to be located in the peripheral area; and optionally, a black matrix is formed on a second substrate disposed opposite to the first substrate for screening the extended portions of the pixel electrodes located in the peripheral area, a rubbing direction of aligning films is formed on the first and the second substrates towards the extended portions of the pixel electrodes located in the peripheral area so that impurity ions on the surface of the aligning film travel along the rubbing direction to stop at the extended portions of the pixel electrode, and an image defect area caused by the impurity ions is screened with the black matrix.
    Type: Grant
    Filed: May 2, 2007
    Date of Patent: March 31, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Suk Chung, Chi-Woo Kim, Bo-Young An, Hyong-Gon Lee, Sung-Hee Cho
  • Publication number: 20080032499
    Abstract: First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300° C. for 5 minutes, and a semiconductor layer an ohmic contact layer are sequentially formed. Next, a conductor layer of a metal such as Cr is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad. Next, indium zinc oxide is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively connected to the drain electrode, the gate pad and the data pad.
    Type: Application
    Filed: October 18, 2007
    Publication date: February 7, 2008
    Inventors: Hyang-Shik KONG, Myung-Koo Hur, Chi-Woo Kim
  • Publication number: 20080030494
    Abstract: A gate-on voltage generation circuit, a gate-off voltage generation circuit, and a liquid crystal display (LCD) using the same are provided. The gate-on voltage generation circuit includes a first capacitor charged with a first control signal and a first reference voltage to output a first charging voltage through a first output node according to the first control signal. A second capacitor is charged with a second control signal and the first reference voltage to output a second charging voltage according to the second control signal. A first switching device is connected between the first capacitor and the first output node to selectively output the first charging voltage to the first output node. A second switching device is turned on by the second charging voltage to supply the first reference voltage to the first capacitor, the first and second switching devices being exclusively turned on and off.
    Type: Application
    Filed: August 1, 2007
    Publication date: February 7, 2008
    Inventors: Doo Hyung Woo, Kee Chan Park, Chi Woo Kim, Shang Min Yhee, Zhangzhifeng, Seong Park
  • Publication number: 20080026500
    Abstract: A flat panel display device includes a substrate including a pixel area having a plurality of pixel parts and a peripheral circuit area disposed adjacent to the pixel area to drive the pixel parts, a circuit TFT disposed in the peripheral circuit area, the circuit TFT including a first semiconductor layer having a first crystal growth in a lateral direction, and a pixel TFT disposed in the pixel area, the pixel TFT including a second semiconductor layer having a second crystal isotropic growth.
    Type: Application
    Filed: July 23, 2007
    Publication date: January 31, 2008
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Han-Na Jo, Chi-Woo Kim, Young-Jin Chang, Jae-Beom Choi
  • Publication number: 20070263129
    Abstract: A display device includes a liquid crystal panel including an upper substrate and a lower substrate facing each other with liquid crystals being disposed therebetween, a first polarizing plate bonded to a front surface of the liquid crystal panel and a touch panel including a lower electrode formed on the upper substrate of the liquid crystal panel and an upper electrode formed on a back surface of the first polarizing plate. The liquid crystal panel further includes a thin film transistor formed on the lower substrate, a pixel electrode connected to the thin film transistor, a color filter formed on the lower substrate and a common electrode formed on the upper substrate and forming an electric field with the pixel electrode.
    Type: Application
    Filed: May 9, 2007
    Publication date: November 15, 2007
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Won Sang Park, Jin Hyuk Yun, Chi Woo Kim, Seok Won Park
  • Patent number: 7288442
    Abstract: First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300° C. for 5 minutes, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer of a metal such as Cr is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad. Next, indium zinc oxide is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively connected to the drain electrode, the gate pad and the data pad.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: October 30, 2007
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Hyang-Shik Kong, Myung-Koo Hur, Chi-Woo Kim
  • Publication number: 20070229747
    Abstract: In a liquid crystal display, a plurality of gate lines and data lines are provided on a first substrate including a display area as a screen, and a peripheral area external to the display area wherein a plurality of pixel electrodes are electrically connected to the gate lines and to the data lines, and some of the pixel electrodes extend to be located in the peripheral area; and optionally, a black matrix is formed on a second substrate disposed opposite to the first substrate for screening the extended portions of the pixel electrodes located in the peripheral area, a rubbing direction of aligning films is formed on the first and the second substrates towards the extended portions of the pixel electrodes located in the peripheral area so that impurity ions on the surface of the aligning film travel along the rubbing direction to stop at the extended portions of the pixel electrode, and an image defect area caused by the impurity ions is screened with the black matrix.
    Type: Application
    Filed: May 2, 2007
    Publication date: October 4, 2007
    Inventors: Woo-Suk Chung, Chi-Woo Kim, Bo-Young An, Hyong-Gon Lee, Sung-Hee Cho
  • Patent number: 7218371
    Abstract: In a liquid crystal display, a plurality of gate lines and data lines are provided on a first substrate including a display area as a screen, and a peripheral area external to the display area wherein a plurality of pixel electrodes are electrically connected to the gate lines and to the data lines, and some of the pixel electrodes extend to be located in the peripheral area; and optionally, a black matrix is formed on a second substrate disposed opposite to the first substrate for screening the extended portions of the pixel electrodes located in the peripheral area, a rubbing direction of aligning films is formed on the first and the second substrates towards the extended portions of the pixel electrodes located in the peripheral area so that impurity ions on the surface of the aligning film travel along the rubbing direction to stop at the extended portions of the pixel electrodes, and an image defect area caused by the impurity ions is screened with the black matrix.
    Type: Grant
    Filed: June 24, 2005
    Date of Patent: May 15, 2007
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Suk Chung, Chi-Woo Kim, Bo-Young An, Hyong-Gon Lee, Sung-Hee Cho
  • Publication number: 20060228908
    Abstract: In a method of manufacturing a polysilicon thin film and a method of manufacturing a TFT having the thin film, a laser beam is irradiated on a portion of an amorphous silicon thin film to liquefy the portion of the amorphous silicon thin film. The amorphous silicon thin film is on a first end portion of a substrate. The liquefied silicon is crystallized to form silicon grains. The laser beam is shifted from the first end portion towards a second end portion of the substrate opposite the first end portion by an interval in a first direction. The laser beam is then irradiated onto a portion of the amorphous silicon thin film adjacent to the silicon grains to form a first polysilicon thin film. Therefore, electrical characteristics of the amorphous silicon thin film may be improved.
    Type: Application
    Filed: September 23, 2005
    Publication date: October 12, 2006
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Se-Jin Chung, Chi-Woo Kim, Ui-Jin Chung, Dong-Byum Kim
  • Publication number: 20060221662
    Abstract: A display device includes a plurality of pixels, wherein each pixel includes: a light emitting element; a first capacitor connected between a first node and a second node; a driving transistor having an input terminal, an output terminal, and a control terminal connected to the second node where the driving transistor supplies a driving current to the light emitting element to emit light; a first switching unit supplying a first reference voltage to the driving transistor according to a first scanning signal and connecting the first node to a data voltage or the driving transistor; and a second switching unit supplying a driving voltage to the driving transistor according to a second scanning signal and connecting the first node to the data voltage. Accordingly, variations in threshold voltage of the driving transistor can be compensated for so that it is possible to display a uniform image.
    Type: Application
    Filed: March 9, 2006
    Publication date: October 5, 2006
    Inventors: Kee-Chan Park, Ho-Suk Maeng, Seong-Il Park, Cheol-Min Kim, Chi-Woo Kim, Soong-Yong Joo, Il-Gon Kim
  • Publication number: 20060001819
    Abstract: A display device includes a circuit board provided with signal lines, a first and a second panel unit separately attached to the circuit board and each provided with pixels comprising switching elements, and a driving circuit chip mounted on the circuit board and driving the first and the second panel units.
    Type: Application
    Filed: June 23, 2005
    Publication date: January 5, 2006
    Inventors: Ho-Suk Maeng, Soong-Yong Joo, Chul-Ho Kim, Kee-Chan Park, Cheol-Min Kim, Tae-Hyeong Park, Kook-Chul Moon, II-Gon Kim, Chi-Woo Kim, Jin-Hyuk Yun
  • Publication number: 20050237466
    Abstract: In a liquid crystal display, a plurality of gate lines and data lines are provided on a first substrate including a display area as a screen, and a peripheral area external to the display area wherein a plurality of pixel electrodes are electrically connected to the gate lines and to the data lines, and some of the pixel electrodes extend to be located in the peripheral area; and optionally, a black matrix is formed on a second substrate disposed opposite to the first substrate for screening the extended portions of the pixel electrodes located in the peripheral area, a rubbing direction of aligning films is formed on the first and the second substrates towards the extended portions of the pixel electrodes located in the peripheral area so that impurity ions on the surface of the aligning film travel along the rubbing direction to stop at the extended portions of the pixel electrodes, and an image defect area caused by the impurity ions is screened with the black matrix.
    Type: Application
    Filed: June 24, 2005
    Publication date: October 27, 2005
    Inventors: Woo-Suk Chung, Chi-Woo Kim, Bo-Young An, Hyong-Gon Lee, Sung-Hee Cho
  • Patent number: 6954244
    Abstract: Disclosed is a reflection type liquid crystal display device. A second substrate (220) is provided opposite to a first substrate (210) where pixels are formed. A liquid crystal layer (230) is interposed between the first and second substrates. A reflection electrode (235) is formed on the first substrate (210). The reflection electrode (235) includes first and second regions (290, 295) having relatively high and low heights so as to scatter a light, respectively. The first regions (290) have first widths in a first direction wider than second widths in a second direction so that a reflectivity in the first direction is higher than a reflectivity in the second direction. The widths of the grooves (290a, b) are varied in a desired direction regardless of shapes of the lenses (295), to thereby improve the viewing angle and reflectivity of the display in the specific direction.
    Type: Grant
    Filed: August 5, 2002
    Date of Patent: October 11, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin Jeon, Chi-Woo Kim
  • Patent number: 6946681
    Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 ??cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.
    Type: Grant
    Filed: December 11, 2003
    Date of Patent: September 20, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Oh Jeong, Yang-Sun Kim, Myung-Koo Hur, Young-Jae Tak, Mun-Pyo Hong, Chi-Woo Kim, Jang-Soo Kim, Chun-Gi You
  • Patent number: 6927830
    Abstract: In a liquid crystal display, a plurality of gate lines and data lines are provided on a first substrate including a display area as a screen, and a peripheral area external to the display area wherein a plurality of pixel electrodes are electrically connected to the gate lines and to the data lines, and some of the pixel electrodes extend to be located in the peripheral area; and optionally, a black matrix is formed on a second substrate disposed opposite to the first substrate for screening the extended portions of the pixel electrodes located in the peripheral area, a rubbing direction of aligning films is formed on the first and the second substrates towards the extended portions of the pixel electrodes located in the peripheral area so that impurity ions on the surface of the aligning film travel along the rubbing direction to stop at the extended portions of the pixel electrodes, and an image defect area caused by the impurity ions is screened with the black matrix.
    Type: Grant
    Filed: June 20, 2002
    Date of Patent: August 9, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Woo-Suk Chung, Chi-Woo Kim, Bo-Young An, Hyong-Gon Lee, Sung-Hee Cho
  • Publication number: 20040140566
    Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.
    Type: Application
    Filed: December 11, 2003
    Publication date: July 22, 2004
    Inventors: Chang-Oh Jeong, Yang-Sun Kim, Myung-Koo Hur, Young-Jae Tak, Mun-Pyo Hong, Chi-Woo Kim, Jang-Soo Kim, Chun-Gi You
  • Publication number: 20040029308
    Abstract: First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300° C. for 5 minutes, and a semiconductor layer an ohmic contact layer are sequentially formed. Next, a conductor layer of a metal such as Cr is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad. Next, indium zinc oxide is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively connected to the drain electrode, the gate pad and the data pad.
    Type: Application
    Filed: August 6, 2003
    Publication date: February 12, 2004
    Inventors: Hyang-Shik Kong, Myung-Koo Hur, Chi-Woo Kim
  • Patent number: 6686606
    Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: February 3, 2004
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chang-Oh Jeong, Yang-Sun Kim, Myung-Koo Hur, Young-Jae Tak, Mun-Pyo Hong, Chi-Woo Kim, Jang-Soo Kim, Chua-Gi You