Patents by Inventor Chi-Woo Kim
Chi-Woo Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7575963Abstract: First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300° C. for 5 minutes, and a semiconductor layer an ohmic contact layer are sequentially formed. Next, a conductor layer of a metal such as Cr is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad. Next, indium zinc oxide is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively connected to the drain electrode, the gate pad and the data pad.Type: GrantFiled: October 18, 2007Date of Patent: August 18, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Hyang-Shik Kong, Myung-Koo Hur, Chi-Woo Kim
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Patent number: 7557050Abstract: In a method of manufacturing a polysilicon thin film and a method of manufacturing a TFT having the thin film, a laser beam is irradiated on a portion of an amorphous silicon thin film to liquefy the portion of the amorphous silicon thin film. The amorphous silicon thin film is on a first end portion of a substrate. The liquefied silicon is crystallized to form silicon grains. The laser beam is shifted from the first end portion towards a second end portion of the substrate opposite the first end portion by an interval in a first direction. The laser beam is then irradiated onto a portion of the amorphous silicon thin film adjacent to the silicon grains to form a first polysilicon thin film. Therefore, electrical characteristics of the amorphous silicon thin film may be improved.Type: GrantFiled: September 23, 2005Date of Patent: July 7, 2009Assignee: Samsung Electroncis Co., Ltd.Inventors: Se-Jin Chung, Chi-Woo Kim, Ui-Jin Chung, Dong-Byum Kim
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Patent number: 7511793Abstract: In a liquid crystal display, a plurality of gate lines and data lines are provided on a first substrate including a display area as a screen, and a peripheral area external to the display area wherein a plurality of pixel electrodes are electrically connected to the gate lines and to the data lines, and some of the pixel electrodes extend to be located in the peripheral area; and optionally, a black matrix is formed on a second substrate disposed opposite to the first substrate for screening the extended portions of the pixel electrodes located in the peripheral area, a rubbing direction of aligning films is formed on the first and the second substrates towards the extended portions of the pixel electrodes located in the peripheral area so that impurity ions on the surface of the aligning film travel along the rubbing direction to stop at the extended portions of the pixel electrode, and an image defect area caused by the impurity ions is screened with the black matrix.Type: GrantFiled: May 2, 2007Date of Patent: March 31, 2009Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-Suk Chung, Chi-Woo Kim, Bo-Young An, Hyong-Gon Lee, Sung-Hee Cho
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Publication number: 20080032499Abstract: First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300° C. for 5 minutes, and a semiconductor layer an ohmic contact layer are sequentially formed. Next, a conductor layer of a metal such as Cr is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad. Next, indium zinc oxide is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively connected to the drain electrode, the gate pad and the data pad.Type: ApplicationFiled: October 18, 2007Publication date: February 7, 2008Inventors: Hyang-Shik KONG, Myung-Koo Hur, Chi-Woo Kim
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Publication number: 20080030494Abstract: A gate-on voltage generation circuit, a gate-off voltage generation circuit, and a liquid crystal display (LCD) using the same are provided. The gate-on voltage generation circuit includes a first capacitor charged with a first control signal and a first reference voltage to output a first charging voltage through a first output node according to the first control signal. A second capacitor is charged with a second control signal and the first reference voltage to output a second charging voltage according to the second control signal. A first switching device is connected between the first capacitor and the first output node to selectively output the first charging voltage to the first output node. A second switching device is turned on by the second charging voltage to supply the first reference voltage to the first capacitor, the first and second switching devices being exclusively turned on and off.Type: ApplicationFiled: August 1, 2007Publication date: February 7, 2008Inventors: Doo Hyung Woo, Kee Chan Park, Chi Woo Kim, Shang Min Yhee, Zhangzhifeng, Seong Park
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Publication number: 20080026500Abstract: A flat panel display device includes a substrate including a pixel area having a plurality of pixel parts and a peripheral circuit area disposed adjacent to the pixel area to drive the pixel parts, a circuit TFT disposed in the peripheral circuit area, the circuit TFT including a first semiconductor layer having a first crystal growth in a lateral direction, and a pixel TFT disposed in the pixel area, the pixel TFT including a second semiconductor layer having a second crystal isotropic growth.Type: ApplicationFiled: July 23, 2007Publication date: January 31, 2008Applicant: Samsung Electronics Co., Ltd.Inventors: Han-Na Jo, Chi-Woo Kim, Young-Jin Chang, Jae-Beom Choi
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Publication number: 20070263129Abstract: A display device includes a liquid crystal panel including an upper substrate and a lower substrate facing each other with liquid crystals being disposed therebetween, a first polarizing plate bonded to a front surface of the liquid crystal panel and a touch panel including a lower electrode formed on the upper substrate of the liquid crystal panel and an upper electrode formed on a back surface of the first polarizing plate. The liquid crystal panel further includes a thin film transistor formed on the lower substrate, a pixel electrode connected to the thin film transistor, a color filter formed on the lower substrate and a common electrode formed on the upper substrate and forming an electric field with the pixel electrode.Type: ApplicationFiled: May 9, 2007Publication date: November 15, 2007Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Won Sang Park, Jin Hyuk Yun, Chi Woo Kim, Seok Won Park
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Patent number: 7288442Abstract: First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300° C. for 5 minutes, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer of a metal such as Cr is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad. Next, indium zinc oxide is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively connected to the drain electrode, the gate pad and the data pad.Type: GrantFiled: August 6, 2003Date of Patent: October 30, 2007Assignee: Samsung Electronics Co., LtdInventors: Hyang-Shik Kong, Myung-Koo Hur, Chi-Woo Kim
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Publication number: 20070229747Abstract: In a liquid crystal display, a plurality of gate lines and data lines are provided on a first substrate including a display area as a screen, and a peripheral area external to the display area wherein a plurality of pixel electrodes are electrically connected to the gate lines and to the data lines, and some of the pixel electrodes extend to be located in the peripheral area; and optionally, a black matrix is formed on a second substrate disposed opposite to the first substrate for screening the extended portions of the pixel electrodes located in the peripheral area, a rubbing direction of aligning films is formed on the first and the second substrates towards the extended portions of the pixel electrodes located in the peripheral area so that impurity ions on the surface of the aligning film travel along the rubbing direction to stop at the extended portions of the pixel electrode, and an image defect area caused by the impurity ions is screened with the black matrix.Type: ApplicationFiled: May 2, 2007Publication date: October 4, 2007Inventors: Woo-Suk Chung, Chi-Woo Kim, Bo-Young An, Hyong-Gon Lee, Sung-Hee Cho
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Patent number: 7218371Abstract: In a liquid crystal display, a plurality of gate lines and data lines are provided on a first substrate including a display area as a screen, and a peripheral area external to the display area wherein a plurality of pixel electrodes are electrically connected to the gate lines and to the data lines, and some of the pixel electrodes extend to be located in the peripheral area; and optionally, a black matrix is formed on a second substrate disposed opposite to the first substrate for screening the extended portions of the pixel electrodes located in the peripheral area, a rubbing direction of aligning films is formed on the first and the second substrates towards the extended portions of the pixel electrodes located in the peripheral area so that impurity ions on the surface of the aligning film travel along the rubbing direction to stop at the extended portions of the pixel electrodes, and an image defect area caused by the impurity ions is screened with the black matrix.Type: GrantFiled: June 24, 2005Date of Patent: May 15, 2007Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-Suk Chung, Chi-Woo Kim, Bo-Young An, Hyong-Gon Lee, Sung-Hee Cho
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Publication number: 20060228908Abstract: In a method of manufacturing a polysilicon thin film and a method of manufacturing a TFT having the thin film, a laser beam is irradiated on a portion of an amorphous silicon thin film to liquefy the portion of the amorphous silicon thin film. The amorphous silicon thin film is on a first end portion of a substrate. The liquefied silicon is crystallized to form silicon grains. The laser beam is shifted from the first end portion towards a second end portion of the substrate opposite the first end portion by an interval in a first direction. The laser beam is then irradiated onto a portion of the amorphous silicon thin film adjacent to the silicon grains to form a first polysilicon thin film. Therefore, electrical characteristics of the amorphous silicon thin film may be improved.Type: ApplicationFiled: September 23, 2005Publication date: October 12, 2006Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Se-Jin Chung, Chi-Woo Kim, Ui-Jin Chung, Dong-Byum Kim
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Publication number: 20060221662Abstract: A display device includes a plurality of pixels, wherein each pixel includes: a light emitting element; a first capacitor connected between a first node and a second node; a driving transistor having an input terminal, an output terminal, and a control terminal connected to the second node where the driving transistor supplies a driving current to the light emitting element to emit light; a first switching unit supplying a first reference voltage to the driving transistor according to a first scanning signal and connecting the first node to a data voltage or the driving transistor; and a second switching unit supplying a driving voltage to the driving transistor according to a second scanning signal and connecting the first node to the data voltage. Accordingly, variations in threshold voltage of the driving transistor can be compensated for so that it is possible to display a uniform image.Type: ApplicationFiled: March 9, 2006Publication date: October 5, 2006Inventors: Kee-Chan Park, Ho-Suk Maeng, Seong-Il Park, Cheol-Min Kim, Chi-Woo Kim, Soong-Yong Joo, Il-Gon Kim
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Publication number: 20060001819Abstract: A display device includes a circuit board provided with signal lines, a first and a second panel unit separately attached to the circuit board and each provided with pixels comprising switching elements, and a driving circuit chip mounted on the circuit board and driving the first and the second panel units.Type: ApplicationFiled: June 23, 2005Publication date: January 5, 2006Inventors: Ho-Suk Maeng, Soong-Yong Joo, Chul-Ho Kim, Kee-Chan Park, Cheol-Min Kim, Tae-Hyeong Park, Kook-Chul Moon, II-Gon Kim, Chi-Woo Kim, Jin-Hyuk Yun
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Publication number: 20050237466Abstract: In a liquid crystal display, a plurality of gate lines and data lines are provided on a first substrate including a display area as a screen, and a peripheral area external to the display area wherein a plurality of pixel electrodes are electrically connected to the gate lines and to the data lines, and some of the pixel electrodes extend to be located in the peripheral area; and optionally, a black matrix is formed on a second substrate disposed opposite to the first substrate for screening the extended portions of the pixel electrodes located in the peripheral area, a rubbing direction of aligning films is formed on the first and the second substrates towards the extended portions of the pixel electrodes located in the peripheral area so that impurity ions on the surface of the aligning film travel along the rubbing direction to stop at the extended portions of the pixel electrodes, and an image defect area caused by the impurity ions is screened with the black matrix.Type: ApplicationFiled: June 24, 2005Publication date: October 27, 2005Inventors: Woo-Suk Chung, Chi-Woo Kim, Bo-Young An, Hyong-Gon Lee, Sung-Hee Cho
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Patent number: 6954244Abstract: Disclosed is a reflection type liquid crystal display device. A second substrate (220) is provided opposite to a first substrate (210) where pixels are formed. A liquid crystal layer (230) is interposed between the first and second substrates. A reflection electrode (235) is formed on the first substrate (210). The reflection electrode (235) includes first and second regions (290, 295) having relatively high and low heights so as to scatter a light, respectively. The first regions (290) have first widths in a first direction wider than second widths in a second direction so that a reflectivity in the first direction is higher than a reflectivity in the second direction. The widths of the grooves (290a, b) are varied in a desired direction regardless of shapes of the lenses (295), to thereby improve the viewing angle and reflectivity of the display in the specific direction.Type: GrantFiled: August 5, 2002Date of Patent: October 11, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Jin Jeon, Chi-Woo Kim
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Patent number: 6946681Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 ??cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.Type: GrantFiled: December 11, 2003Date of Patent: September 20, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Oh Jeong, Yang-Sun Kim, Myung-Koo Hur, Young-Jae Tak, Mun-Pyo Hong, Chi-Woo Kim, Jang-Soo Kim, Chun-Gi You
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Patent number: 6927830Abstract: In a liquid crystal display, a plurality of gate lines and data lines are provided on a first substrate including a display area as a screen, and a peripheral area external to the display area wherein a plurality of pixel electrodes are electrically connected to the gate lines and to the data lines, and some of the pixel electrodes extend to be located in the peripheral area; and optionally, a black matrix is formed on a second substrate disposed opposite to the first substrate for screening the extended portions of the pixel electrodes located in the peripheral area, a rubbing direction of aligning films is formed on the first and the second substrates towards the extended portions of the pixel electrodes located in the peripheral area so that impurity ions on the surface of the aligning film travel along the rubbing direction to stop at the extended portions of the pixel electrodes, and an image defect area caused by the impurity ions is screened with the black matrix.Type: GrantFiled: June 20, 2002Date of Patent: August 9, 2005Assignee: Samsung Electronics Co., Ltd.Inventors: Woo-Suk Chung, Chi-Woo Kim, Bo-Young An, Hyong-Gon Lee, Sung-Hee Cho
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Publication number: 20040140566Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.Type: ApplicationFiled: December 11, 2003Publication date: July 22, 2004Inventors: Chang-Oh Jeong, Yang-Sun Kim, Myung-Koo Hur, Young-Jae Tak, Mun-Pyo Hong, Chi-Woo Kim, Jang-Soo Kim, Chun-Gi You
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Publication number: 20040029308Abstract: First, a conductive material of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed by depositing nitride silicon in the range of more than 300° C. for 5 minutes, and a semiconductor layer an ohmic contact layer are sequentially formed. Next, a conductor layer of a metal such as Cr is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad. Next, indium zinc oxide is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively connected to the drain electrode, the gate pad and the data pad.Type: ApplicationFiled: August 6, 2003Publication date: February 12, 2004Inventors: Hyang-Shik Kong, Myung-Koo Hur, Chi-Woo Kim
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Patent number: 6686606Abstract: The Mo or MoW composition layer has a low resistivity of less than 15 &mgr;&OHgr;cm and is etched to have a smooth taper angle using an Al alloy enchant or a Cr enchant, and the Mo or MoW layer is used for a wiring of a display or a semiconductor display along with an Al layer or a Cr layer. Since the Mo or MoW layer can be deposited so as to give low stress to the substrate by adjusting the deposition pressure, a single MoW layer can be used as a wiring by itself. When contact holes are formed in the passivation layer or the gate insulating layer, a lateral etch is reduced by using polymer layer, an etch gas system using CF4+O2 can prevent the etch of the Mo or MoW alloy layer, and an etch gas of SF6+HCl (+He) or SF6+Cl2 (+He) can form the edge profile of contact holes to be smoothed.Type: GrantFiled: March 18, 2003Date of Patent: February 3, 2004Assignee: Samsung Electronics Co., Ltd.Inventors: Chang-Oh Jeong, Yang-Sun Kim, Myung-Koo Hur, Young-Jae Tak, Mun-Pyo Hong, Chi-Woo Kim, Jang-Soo Kim, Chua-Gi You