Patents by Inventor Chi-Yu Wang

Chi-Yu Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7071544
    Abstract: A wafer level package mainly comprises a semiconductor wafer and a plurality of bonding pads disposed on the active surface of the wafer. It is characterized in that there is a protection layer formed on the back surface of the wafer, wherein the wettability of the solder material with the protection layer is lower than the wettability of the solder material with the bonding pads. In such a manner, the protection layer will prevent the back surface of the wafer from being contaminated with the solder material. Moreover, when a UBM layer is further provided on the bonding pad, the wettability of the solder material with the protection layer is lower than the wettability of the solder material with the UBM layer.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: July 4, 2006
    Assignee: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi-Yu Wang, Tai-Yuan Huang
  • Publication number: 20060103020
    Abstract: A circuit structure of a redistribution layer (RDL) is suitable for a chip to define the circuits and the contact window required by the following bump process. The RDL is disposed on the active surface of the chip. The circuit structure of the RDL mainly includes a first titanium layer, a second titanium layer and a conductive layer. Wherein, the conductive layer is made of aluminum; the first titanium layer and the second titanium layer cover the two surfaces of the conductive layer, respectively. The connectivity between the first titanium layer or the second titanium layer and a macromolecule polymer is stronger than the connectivity between the conductive layer and the macromolecule polymer, so that the peeling or crack caused by poor connectivity between the conductive layer and the adjacent dielectric layers are significantly improved thereby.
    Type: Application
    Filed: October 31, 2005
    Publication date: May 18, 2006
    Inventors: Ho-Ming Tong, Shin-Hua Chao, Chi-Yu Wang, Cherry Mercado Reyes
  • Publication number: 20040150119
    Abstract: A wafer level package mainly comprises a semiconductor wafer and a plurality of bonding pads disposed on the active surface of the wafer. It is characterized in that there is a protection layer formed on the back surface of the wafer, wherein the wettability of the solder material with the protection layer is lower than the wettability of the solder material with the bonding pads. In such a manner, the protection layer will prevent the back surface of the wafer from being contaminated with the solder material. Moreover, when a UBM layer is further provided on the bonding pad, the wettability of the solder material with the protection layer is lower than the wettability of the solder material with the UBM layer.
    Type: Application
    Filed: December 30, 2003
    Publication date: August 5, 2004
    Applicant: Advanced Semiconductor Engineering, Inc.
    Inventors: Chi-Yu Wang, Tai-Yuan Huang