Abstract: The present invention relates a method of controlling and monitoring the thickness variation of the film structure of a semiconductor wafer by monitoring the thickness variation of the film structure of a testing region. The method is characterized by etching the film structure of the testing region with a pattern density substantially compatible with that of the device region in order to precisely simulate the thickness variation of the film structure of a device region in a chemical mechanical polishing process.

Abstract: A method and a circuit layout on a substrate of a semiconductor wafer, suitable for reducing defects during a chemical mechanical polishing process. On the substrate, the circuit layout comprises a plurality of strips of first circuit structure and at least two strips of second circuit structure located on the substrate. Each of the strips of second circuit structure respectively links the front end and the rear end of the plurality of strips of the first circuit structure for the purpose of averaging polishing pressure performed upon the front end and the rear end of the plurality of strips of the first circuit structure during the chemical mechanical polishing process for reducing defects.

Abstract: A ratchet tool includes a ring-shaped head having a toothed member rotatably received therein and a first end of a handle is pivotally inserted in the ring-shaped head. A pawl is connected to the first end of the handle and pivotally engaged with the toothed member. Two springs are received in the ring-shaped head and contact two sides of the handle.

Abstract: The method of forming a plurality of contact holes on a semiconductor substrate using multiple-step etching process is disclosed herein. A semiconductor substrate is provided having a plurality of semiconductor devices and a plurality of isolation regions formed thereon. A silicon oxide layer is formed on the plurality of semiconductor devices, the plurality of isolation regions, and the semiconductor substrate. An etching stop layer is formed on the silicon oxide layer followed by depositing an interlevel dielectric layer. A photoresist layer is pattern on the interlevel dielectric layer to define contact regions. A first etching process is performed to create a plurality of contact holes in the interlevel dielectric layer until exposing portions of the etching stop layer. A second etching process is performed to create the plurality of contact holes through the etching stop layer.

Abstract: A ratchet tool includes a ring-shaped head and a ring member is rotatably received in the ring-shaped head and a toothed outer periphery of the ring member is engaged with a pawl which is movably received in a recess in an inner periphery of the ring-shaped head. A protrusion extends from a top of the pawl and is retained in a notch of a plate from which two rods extend. A positioning ring is engaged with the ring-shaped head and has a slot so that the two rods extend through the slot. A lever has a head which has two holes so as to receive the two rods of the plate. The pawl can be shifted to engage with the ring member by pushing the lever. Two curve surfaces are defined in the two ends of the pawl and one of which is engaged with a curve surface defining the curve recess. The number of contact teeth between the ring member and the pawl is increased.

Abstract: An array multiplier using modified Booth encoding of multiplier input signals is formed on the surface of a monolithic integrated circuit using masks generated by a computer, in accordance with a silicon compiler program, by arranging an array of standard cells selected from a library of standard cell designs in a tessellation procedure. The array multiplier is laid out in accordance with one of particular tessellation patterns, which employ simpler and more regular patterns of interconnections between cells. Carry-save addition is used in combining partial product terms to avoid concatenating long ripple carry times.