Patents by Inventor Chi-Yuan Sun
Chi-Yuan Sun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11846881Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, a photo catalytic layer disposed on the capping layer, and an absorber layer disposed on the photo catalytic layer and carrying circuit patterns having openings. Part of the photo catalytic layer is exposed at the openings of the absorber layer, and the photo catalytic layer includes one selected from the group consisting of titanium oxide (TiO2), tin oxide (SnO), zinc oxide (ZnO) and cadmium sulfide (CdS).Type: GrantFiled: July 27, 2022Date of Patent: December 19, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Ching-Huang Chen, Chi-Yuan Sun, Hua-Tai Lin, Hsin-Chang Lee, Ming-Wei Chen
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Publication number: 20220373876Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, a photo catalytic layer disposed on the capping layer, and an absorber layer disposed on the photo catalytic layer and carrying circuit patterns having openings. Part of the photo catalytic layer is exposed at the openings of the absorber layer, and the photo catalytic layer includes one selected from the group consisting of titanium oxide (TiO2), tin oxide (SnO), zinc oxide (ZnO) and cadmium sulfide (CdS).Type: ApplicationFiled: July 27, 2022Publication date: November 24, 2022Inventors: Ching-Huang CHEN, Chi-Yuan SUN, Hua-Tai LIN, Hsin-Chang LEE, Ming-Wei CHEN
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Patent number: 11448956Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, a photo catalytic layer disposed on the capping layer, and an absorber layer disposed on the photo catalytic layer and carrying circuit patterns having openings. Part of the photo catalytic layer is exposed at the openings of the absorber layer, and the photo catalytic layer includes one selected from the group consisting of titanium oxide (TiO2), tin oxide (SnO), zinc oxide (ZnO) and cadmium sulfide (CdS).Type: GrantFiled: September 5, 2019Date of Patent: September 20, 2022Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ching-Huang Chen, Chi-Yuan Sun, Hua-Tai Lin, Hsin-Chang Lee, Ming-Wei Chen
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Publication number: 20210270751Abstract: In a method for inspecting pattern defects, a plurality of patterns are formed over an underlying layer. The plurality of patterns are electrically isolated from each other. A part of the plurality of patterns are scanned with an electron beam to charge the plurality of patterns. An intensity of secondary electrons emitted from the scanned part of the plurality of patterns is obtained. One or more of the plurality of patterns that show an intensity of the secondary electrons different from others of the plurality of patterns are searched.Type: ApplicationFiled: October 29, 2020Publication date: September 2, 2021Inventors: Ju-Ying CHEN, Che-Yen LEE, Chia-Fong CHANG, Hua-Tai LIN, Te-Chih HUANG, Chi-Yuan SUN, Jiann Yuan HUANG
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Publication number: 20210072633Abstract: A reflective mask includes a substrate, a reflective multilayer disposed on the substrate, a capping layer disposed on the reflective multilayer, a photo catalytic layer disposed on the capping layer, and an absorber layer disposed on the photo catalytic layer and carrying circuit patterns having openings. Part of the photo catalytic layer is exposed at the openings of the absorber layer, and the photo catalytic layer includes one selected from the group consisting of titanium oxide (TiO2), tin oxide (SnO), zinc oxide (ZnO) and cadmium sulfide (CdS).Type: ApplicationFiled: September 5, 2019Publication date: March 11, 2021Inventors: Ching-Huang CHEN, Chi-Yuan SUN, Hua-Tai LIN, Hsin-Chang LEE, Ming-Wei CHEN
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Patent number: 10274818Abstract: A photolithography system includes a substrate stage for holding a workpiece, and a mask having main patterns and sub-resolution assistant patterns. The system further includes a diffractive optical element (DOE) for directing a radiation having an aerial image of the main patterns onto the workpiece. The DOE includes a first pair of poles that is positioned symmetrically about a center of the DOE along a first direction. The main patterns are oriented lengthwise along a second direction that is perpendicular to the first direction. The sub-resolution assistant patterns are oriented lengthwise along the first direction.Type: GrantFiled: June 9, 2017Date of Patent: April 30, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Hua-Tai Lin, Yu-Chuan Yang, Wen-Ta Liang, Ching-Huang Chen, Chi-Yuan Sun, Shih-Che Wang
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Patent number: 10199228Abstract: A manufacturing method of a metal gate structure includes the following steps. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. The silicon-containing work function layer includes a vertical portion and a horizontal portion. Finally, the gate trench is filled up with a conductive metal layer.Type: GrantFiled: April 5, 2017Date of Patent: February 5, 2019Assignee: UNITED MICROELECTRONICS CORP.Inventors: Nien-Ting Ho, Chien-Hao Chen, Hsin-Fu Huang, Chi-Yuan Sun, Wei-Yu Chen, Min-Chuan Tsai, Tsun-Min Cheng, Chi-Mao Hsu
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Publication number: 20180174839Abstract: A photolithography system includes a substrate stage for holding a workpiece, and a mask having main patterns and sub-resolution assistant patterns. The system further includes a diffractive optical element (DOE) for directing a radiation having an aerial image of the main patterns onto the workpiece. The DOE includes a first pair of poles that is positioned symmetrically about a center of the DOE along a first direction. The main patterns are oriented lengthwise along a second direction that is perpendicular to the first direction. The sub-resolution assistant patterns are oriented lengthwise along the first direction.Type: ApplicationFiled: June 9, 2017Publication date: June 21, 2018Inventors: Hua-Tai Lin, Yu-Chuan Yang, Wen-Ta Liang, Ching-Huang Chen, Chi-Yuan Sun, Shih-Che Wang
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Publication number: 20170207093Abstract: A manufacturing method of a metal gate structure includes the following steps. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. The silicon-containing work function layer includes a vertical portion and a horizontal portion. Finally, the gate trench is filled up with a conductive metal layer.Type: ApplicationFiled: April 5, 2017Publication date: July 20, 2017Inventors: Nien-Ting Ho, Chien-Hao Chen, Hsin-Fu Huang, Chi-Yuan Sun, Wei-Yu Chen, Min-Chuan Tsai, Tsun-Min Cheng, Chi-Mao Hsu
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Patent number: 9703918Abstract: A method of optimizing a semiconductor mask layout is provided. The method includes accessing a digital file comprising the semiconductor mask layout, accessing processing condition parameters describing process conditions, receiving a request from a user of a mask layout system to initiate a semiconductor mask layout optimization process, applying a set of rules to insert an array of assist features into the semiconductor mask layout, and updating the digital file. The semiconductor mask layout includes a plurality of parallel mask features, wherein pairs of the parallel mask features share an end-to-end region between the parallel mask features of each pair, with an imaginary axis bisecting the end-to-end regions. Each assist feature is located proximate to at least one end-to-end region, and the imaginary axis intersects each assist feature. Related photomasks, design layout systems, and computer-readable media are also provided.Type: GrantFiled: March 16, 2015Date of Patent: July 11, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Wei-De Ho, Chi-Yuan Sun, Ya Hui Chang, Hung-Chang Hsieh
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Patent number: 9653300Abstract: A manufacturing method of a metal gate structure is provided. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. Finally, the gate trench is filled up with a conductive metal layer.Type: GrantFiled: April 16, 2013Date of Patent: May 16, 2017Assignee: UNITED MICROELECTRONICS CORP.Inventors: Nien-Ting Ho, Chien-Hao Chen, Hsin-Fu Huang, Chi-Yuan Sun, Wei-Yu Chen, Min-Chuan Tsai, Tsun-Min Cheng, Chi-Mao Hsu
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Publication number: 20160274455Abstract: A method of optimizing a semiconductor mask layout is provided. The method includes accessing a digital file comprising the semiconductor mask layout, accessing processing condition parameters describing process conditions, receiving a request from a user of a mask layout system to initiate a semiconductor mask layout optimization process, applying a set of rules to insert an array of assist features into the semiconductor mask layout, and updating the digital file. The semiconductor mask layout includes a plurality of parallel mask features, wherein pairs of the parallel mask features share an end-to-end region between the parallel mask features of each pair, with an imaginary axis bisecting the end-to-end regions. Each assist feature is located proximate to at least one end-to-end region, and the imaginary axis intersects each assist feature. Related photomasks, design layout systems, and computer-readable media are also provided.Type: ApplicationFiled: March 16, 2015Publication date: September 22, 2016Inventors: Ho Wei-De, Chi-Yuan Sun, Ya Hui Chang, Hung-Chang Hsieh
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Patent number: 9076784Abstract: A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. A semiconductor process forming said semiconductor structure is also provided.Type: GrantFiled: August 8, 2014Date of Patent: July 7, 2015Assignee: UNITED MICROELECTRONICS CORP.Inventors: Min-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu, Chin-Fu Lin, Chien-Hao Chen, Wei-Yu Chen, Chi-Yuan Sun, Ya-Hsueh Hsieh, Tsun-Min Cheng
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Patent number: 8975666Abstract: A MOS transistor includes a gate structure on a substrate, and the gate structure includes a wetting layer, a transitional layer and a low resistivity material from bottom to top, wherein the transitional layer has the properties of a work function layer, and the gate structure does not have any work function layers. Moreover, the present invention provides a MOS transistor process forming said MOS transistor.Type: GrantFiled: August 22, 2012Date of Patent: March 10, 2015Assignee: United Microelectronics Corp.Inventors: Ya-Hsueh Hsieh, Chi-Mao Hsu, Hsin-Fu Huang, Min-Chuan Tsai, Chien-Hao Chen, Chi-Yuan Sun, Wei-Yu Chen, Chin-Fu Lin
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Publication number: 20150061042Abstract: A metal gate structure is provided. The metal gate structure includes a semiconductor substrate, a gate dielectric layer, a multi-layered P-type work function layer and a conductive metal layer. The gate dielectric layer is disposed on the semiconductor substrate. The multi-layered P-type work function layer is disposed on the gate dielectric layer, and the multi-layered P-type work function layer includes at least a crystalline P-type work function layer and at least an amorphous P-type work function layer. Furthermore, the conductive metal layer is disposed on the multi-layered P-type work function layer.Type: ApplicationFiled: September 3, 2013Publication date: March 5, 2015Applicant: UNITED MICROELECTRONICS CORP.Inventors: Tsun-Min Cheng, Nien-Ting Ho, Chien-Hao Chen, Ching-Yun Chang, Hsin-Fu Huang, Min-Chuan Tsai, Chi-Yuan Sun, Chi-Mao Hsu
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Publication number: 20140346616Abstract: A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. A semiconductor process forming said semiconductor structure is also provided.Type: ApplicationFiled: August 8, 2014Publication date: November 27, 2014Inventors: Min-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu, Chin-Fu Lin, Chien-Hao Chen, Wei-Yu Chen, Chi-Yuan Sun, Ya-Hsueh Hsieh, Tsun-Min Cheng
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Publication number: 20140306273Abstract: A manufacturing method of a metal gate structure is provided. First, a substrate covered by an interlayer dielectric is provided. A gate trench is formed in the interlayer dielectric, wherein a gate dielectric layer is formed in the gate trench. A silicon-containing work function layer is formed on the gate dielectric layer in the gate trench. Finally, the gate trench is filled up with a conductive metal layer.Type: ApplicationFiled: April 16, 2013Publication date: October 16, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Nien-Ting Ho, Chien-Hao Chen, Hsin-Fu Huang, Chi-Yuan Sun, Wei-Yu Chen, Min-Chuan Tsai, Tsun-Min Cheng, Chi-Mao Hsu
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Patent number: 8836049Abstract: A semiconductor structure includes a work function metal layer, a (work function) metal oxide layer and a main electrode. The work function metal layer is located on a substrate. The (work function) metal oxide layer is located on the work function metal layer. The main electrode is located on the (work function) metal oxide layer. Moreover a semiconductor process forming said semiconductor structure is also provided.Type: GrantFiled: June 13, 2012Date of Patent: September 16, 2014Assignee: United Microelectronics Corp.Inventors: Min-Chuan Tsai, Hsin-Fu Huang, Chi-Mao Hsu, Chin-Fu Lin, Chien-Hao Chen, Wei-Yu Chen, Chi-Yuan Sun, Ya-Hsueh Hsieh, Tsun-Min Cheng
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Publication number: 20140239419Abstract: A method of manufacturing a semiconductor device is provided. A silicon substrate is provided, and a gate insulating layer is formed on the silicon substrate. Then, a silicon barrier layer is formed on the gate insulating layer by the physical vapor deposition (PVD) process. Next, a silicon-containing layer is formed on the silicon barrier layer. The silicon barrier layer of the embodiment is a hydrogen-substantial-zero silicon layer, which has a hydrogen concentration of zero substantially.Type: ApplicationFiled: February 27, 2013Publication date: August 28, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chien-Hao Chen, Hsin-Fu Huang, Chi-Yuan Sun, Min-Chuan Tsai, Wei-Yu Chen, Nien-Ting Ho, Tsun-Min Cheng, Chi-Mao Hsu
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Patent number: 8735269Abstract: The method for forming a semiconductor structure includes first providing a substrate. Then, a TiN layer is formed on the substrate at a rate between 0.3 and 0.8 angstrom/second. Finally, a poly-silicon layer is formed directly on the TiN layer. Since the TiN in the barrier layer is formed at a low rate so as to obtain a good quality, the defects in the TiN layer or the defects on the above layer, such as gate dummy layer or gate cap layer, can be avoided.Type: GrantFiled: January 15, 2013Date of Patent: May 27, 2014Assignee: United Microelectronics Corp.Inventors: Chi-Yuan Sun, Chien-Hao Chen, Hsin-Fu Huang, Min-Chuan Tsai, Wei-Yu Chen, Chi-Mao Hsu, Tsun-Min Cheng, Chin-Fu Lin