Abstract: The present disclosure relates to an integrated chip that has a light sensing element arranged within a substrate. An absorption enhancement structure is arranged along a back-side of the substrate, and an interconnect structure is arranged along a front-side of the substrate. A reflection structure includes a dielectric structure and a plurality of semiconductor pillars that matingly engage the dielectric structure. The dielectric structure and semiconductor pillars are arranged along the front-side of the substrate and are spaced between the light sensing element and the interconnect structure. The plurality of semiconductor pillars and the dielectric structure are collectively configured to reflect incident light that has passed through the absorption enhancement structure and through the light sensing element back towards the light sensing element before the incident light strikes the interconnect structure.

Abstract: An embodiment of the disclosure provides a light source apparatus including a light-emitting module and a control unit. The light-emitting module is configured to provide a light. The control unit is configured to change proportion of a first sub-light and a second sub-light to form the light so that a circadian action factor (CAF) and a correlated color temperature (CCT) of the light varies along a CAF vs. CCT locus of the light different from a CAF vs. CCT locus of sunlight. A CAF vs. CCT coordinate of one of the first sub-light and the second sub-light is below the CAF vs. CCT locus of sunlight, and a CAF vs. CCT coordinate of the other one of the first sub-light and the second sub-light is above the CAF vs. CCT locus of sunlight. A display apparatus is also provided.

Abstract: The present disclosure relates to an integrated chip that has a light sensing element arranged within a substrate. An absorption enhancement structure is arranged along a back-side of the substrate, and an interconnect structure is arranged along a front-side of the substrate. A reflection structure includes a dielectric structure and a plurality of semiconductor pillars that matingly engage the dielectric structure. The dielectric structure and semiconductor pillars are arranged along the front-side of the substrate and are spaced between the light sensing element and the interconnect structure. The plurality of semiconductor pillars and the dielectric structure are collectively configured to reflect incident light that has passed through the absorption enhancement structure and through the light sensing element back towards the light sensing element before the incident light strikes the interconnect structure.

Abstract: The present disclosure relates to an integrated chip that has a light sensing element arranged within a substrate. An absorption enhancement structure is arranged along a back-side of the substrate, and an interconnect structure is arranged along a front-side of the substrate. A reflection structure includes a dielectric structure and a plurality of semiconductor pillars that matingly engage the dielectric structure. The dielectric structure and semiconductor pillars are arranged along the front-side of the substrate and are spaced between the light sensing element and the interconnect structure. The plurality of semiconductor pillars and the dielectric structure are collectively configured to reflect incident light that has passed through the absorption enhancement structure and through the light sensing element back towards the light sensing element before the incident light strikes the interconnect structure.

Abstract: An embodiment of the disclosure provides a light source apparatus including a light-emitting module and a control unit. The light-emitting module is configured to provide a light. The control unit is configured to change proportion of a first sub-light and a second sub-light to form the light so that a circadian action factor (CAF) and a correlated color temperature (CCT) of the light varies along a CAF vs. CCT locus of the light different from a CAF vs. CCT locus of sunlight. A CAF vs. CCT coordinate of one of the first sub-light and the second sub-light is below the CAF vs. CCT locus of sunlight, and a CAF vs. CCT coordinate of the other one of the first sub-light and the second sub-light is above the CAF vs. CCT locus of sunlight. A display apparatus is also provided.

Abstract: The present disclosure relates to an integrated chip that has a light sensing element arranged within a substrate. An absorption enhancement structure is arranged along a back-side of the substrate, and an interconnect structure is arranged along a front-side of the substrate. A reflection structure includes a dielectric structure and a plurality of semiconductor pillars that matingly engage the dielectric structure. The dielectric structure and semiconductor pillars are arranged along the front-side of the substrate and are spaced between the light sensing element and the interconnect structure. The plurality of semiconductor pillars and the dielectric structure are collectively configured to reflect incident light that has passed through the absorption enhancement structure and through the light sensing element back towards the light sensing element before the incident light strikes the interconnect structure.

Abstract: The present disclosure relates to an integrated chip that has a light sensing element arranged within a substrate. An absorption enhancement structure is arranged along a back-side of the substrate, and an interconnect structure is arranged along a front-side of the substrate. A reflection structure includes a dielectric structure and a plurality of semiconductor pillars that matingly engage the dielectric structure. The dielectric structure and semiconductor pillars are arranged along the front-side of the substrate and are spaced between the light sensing element and the interconnect structure. The plurality of semiconductor pillars and the dielectric structure are collectively configured to reflect incident light that has passed through the absorption enhancement structure and through the light sensing element back towards the light sensing element before the incident light strikes the interconnect structure.

Abstract: A semiconductor structure includes a semiconductive substrate including a first surface and a second surface opposite to the first surface, a shallow trench isolation (STI) including a first portion at least partially disposed within the semiconductive substrate and tapered from the first surface towards the second surface, and a second portion disposed inside the semiconductive substrate, coupled with the first portion and extended from the first portion towards the second surface, and a void enclosed by the STI, wherein the void is at least partially disposed within the second portion of the STI.

Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate having a front surface, a back surface opposite to the front surface, at least one light-sensing region close to the front surface, and a first trench surrounding the light-sensing region. The first trench has an inner wall and a bottom surface. The image sensor device includes an insulating layer covering the back surface, the inner wall, and the bottom surface. A thickness of a first upper portion of the insulating layer in the first trench increases in a direction away from the front surface, and the insulating layer has a second trench partially in the first trench. The image sensor device includes a reflective structure filled in the second trench. The reflective structure has a light reflectivity ranging from about 70% to about 100%.

Abstract: An image sensor device is provided. The image sensor device includes a semiconductor substrate having a front surface, a back surface opposite to the front surface, at least one light-sensing region close to the front surface, and a first trench surrounding the light-sensing region. The first trench has an inner wall and a bottom surface. The image sensor device includes an insulating layer covering the back surface, the inner wall, and the bottom surface. A thickness of a first upper portion of the insulating layer in the first trench increases in a direction away from the front surface, and the insulating layer has a second trench partially in the first trench. The image sensor device includes a reflective structure filled in the second trench. The reflective structure has a light reflectivity ranging from about 70% to about 100%.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an image sensor integrated chip. The method may be performed by forming an image sensing element within a substrate, and forming an absorption enhancement structure over a back-side of the substrate. The absorption enhancement structure is selectively etched to concurrently define a plurality of grid structure openings and a ground structure opening within the absorption enhancement structure. A grid structure is formed within the plurality of grid structure openings and a ground structure is formed within the ground structure opening. The grid structure extends from over the absorption enhancement structure to a location within the absorption enhancement structure.

Abstract: A semiconductor structure includes a semiconductive substrate including a first surface and a second surface opposite to the first surface, a shallow trench isolation (STI) including a first portion at least partially disposed within the semiconductive substrate and tapered from the first surface towards the second surface, and a second portion disposed inside the semiconductive substrate, coupled with the first portion and extended from the first portion towards the second surface, and a void enclosed by the STI, wherein the void is at least partially disposed within the second portion of the STI.

Abstract: The present disclosure, in some embodiments, relates to a method of forming an image sensor integrated chip. The method may be performed by forming an image sensing element within a substrate, and forming an absorption enhancement structure over a back-side of the substrate. The absorption enhancement structure is selectively etched to concurrently define a plurality of grid structure openings and a ground structure opening within the absorption enhancement structure. A grid structure is formed within the plurality of grid structure openings and a ground structure is formed within the ground structure opening. The grid structure extends from over the absorption enhancement structure to a location within the absorption enhancement structure.

Abstract: An FSI image sensor device structure is provided. The FSI image sensor device structure includes a substrate and a barrier structure formed in the substrate. The barrier structure includes a plurality of protrusion portions and a plurality of pillar portions. Each of the protrusion portions has a first height, and each of the pillar portions has a second height that is greater than the first height. The FSI image sensor device structure includes a pixel region formed over the protrusion portions and a storage region formed over the protrusion portions, wherein the pillar portions surround the pixel region.

Abstract: The present disclosure relates to an image sensor integrated chip having a grid structure that reduces crosstalk between pixel regions of an image sensor chip. In some embodiments, the integrated chip has an image sensing element arranged within a substrate. An absorption enhancement structure is disposed along the back-side of the substrate. A grid structure is arranged over the absorption enhancement structure. The grid structure defines an opening arranged over the image sensing element and extends from over the absorption enhancement structure to a location within the absorption enhancement structure. By having the grid structure extend into the absorption enhancement structure, the grid structure is able to reduce crosstalk between adjacent image sensing elements by blocking radiation reflected off of non-planar surfaces of the absorption enhancement structure from traveling to an adjacent pixel region.

Abstract: The present disclosure relates to an integrated chip that has a light sensing element arranged within a substrate. An absorption enhancement structure is arranged along a back-side of the substrate, and an interconnect structure is arranged along a front-side of the substrate. A reflection structure includes a dielectric structure and a plurality of semiconductor pillars that matingly engage the dielectric structure. The dielectric structure and semiconductor pillars are arranged along the front-side of the substrate and are spaced between the light sensing element and the interconnect structure. The plurality of semiconductor pillars and the dielectric structure are collectively configured to reflect incident light that has passed through the absorption enhancement structure and through the light sensing element back towards the light sensing element before the incident light strikes the interconnect structure.

Abstract: The present disclosure relates to an image sensor integrated chip having a grid structure that reduces crosstalk between pixel regions of an image sensor chip. In some embodiments, the integrated chip has an image sensing element arranged within a substrate. An absorption enhancement structure is disposed along the back-side of the substrate. A grid structure is arranged over the absorption enhancement structure. The grid structure defines an opening arranged over the image sensing element and extends from over the absorption enhancement structure to a location within the absorption enhancement structure. By having the grid structure extend into the absorption enhancement structure, the grid structure is able to reduce crosstalk between adjacent image sensing elements by blocking radiation reflected off of non-planar surfaces of the absorption enhancement structure from traveling to an adjacent pixel region.

Abstract: A semiconductor structure includes a semiconductive substrate including a first surface and a second surface opposite to the first surface, a shallow trench isolation (STI) including a first portion at least partially disposed within the semiconductive substrate and tapered from the first surface towards the second surface, and a second portion disposed inside the semiconductive substrate, coupled with the first portion and extended from the first portion towards the second surface, and a void enclosed by the STI, wherein the void is at least partially disposed within the second portion of the STI.

Abstract: A semiconductor structure includes a semiconductive substrate including a first surface and a second surface opposite to the first surface, a shallow trench isolation (STI) including a first portion at least partially disposed within the semiconductive substrate and tapered from the first surface towards the second surface, and a second portion disposed inside the semiconductive substrate, coupled with the first portion and extended from the first portion towards the second surface, and a void enclosed by the STI, wherein the void is at least partially disposed within the second portion of the STI.

Abstract: A semiconductor structure is provided, which includes a semiconductor substrate, a first well region, a second well region, an active region, a shallow trench isolation (STI) and at least one deep trench isolation (DTI). The first well region of a first conductive type is on the semiconductor substrate. The second well region of a second conductive type is on the semiconductor substrate and adjacent to the first well region. The second conductive type is different from the first conductive type. The active region is on the first well region. The active region has a conductive type the same as the second conductive type of the second well region. The STI is between the first and second well regions. The DTI is below the STI. The DTI is disposed between at least a portion of the first well region and at least a portion of the second well region.