Patents by Inventor Chia-Chan Chen
Chia-Chan Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11139212Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first conductive element over a substrate and a second conductive element over the substrate. A dielectric region is over a top surface of the substrate and between the first conductive element and the second conductive element. An electrically conductive structure is over the first conductive element, the second conductive element, and the dielectric region.Type: GrantFiled: September 20, 2019Date of Patent: October 5, 2021Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Yueh-Chuan Lee, Chia-Chan Chen
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Patent number: 11133340Abstract: A photosensor device and the method of making the same are provided. In one embodiment, the device includes at least one pixel cell. The at least one pixel cell includes a substrate formed from a semiconductor material, and includes first and second photosensor regions. The first photosensor region is disposed in the substrate and includes a first dopant of a first conductivity type. The second photosensor region is disposed above the first photosensor region and includes a second dopant of a second conductivity type. The second photosensor region can have an increase in dopant concentration from an outer edge to a center portion therein.Type: GrantFiled: December 5, 2019Date of Patent: September 28, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Chan Chen, Yueh-Chuan Lee, Ta-Hsin Chen, Shih-Hsien Huang, Chih-Huang Li
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Publication number: 20210265403Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a photodetector region provided in a substrate. A dielectric material is disposed within a trench defined by one or more interior surfaces of the substrate. The trench has a depth that extends from an upper surface of the substrate to within the substrate. A doped silicon material is disposed within the trench and has a sidewall facing away from the doped silicon material. The sidewall contacts a sidewall of the dielectric material along an interface extending along the depth of the trench.Type: ApplicationFiled: April 29, 2021Publication date: August 26, 2021Inventors: Yueh-Chuan Lee, Chia-Chan Chen
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Publication number: 20210217803Abstract: A method includes at least the following steps. A material layer is formed over an image capture chip. A patterned mask layer is formed on the material layer, wherein a pattern density of the patterned mask layer varies from a central region of the patterned mask layer to a periphery region of the patterned mask layer. The material layer is polished by using the patterned mask layer as a mask to form a lens layer including a single lens portion on the image capture chip.Type: ApplicationFiled: January 15, 2020Publication date: July 15, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Chia-Chan Chen
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Publication number: 20210193718Abstract: A photo-sensing device includes a semiconductor substrate, a photosensitive device, a dielectric layer and a light pipe. The photosensitive device is in the semiconductor substrate. The dielectric layer is over the semiconductor substrate. The light pipe is over the photosensitive device and embedded in the dielectric layer. The light pipe includes a curved and convex light-incident surface.Type: ApplicationFiled: December 19, 2019Publication date: June 24, 2021Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Chia-Chan Chen
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Patent number: 10998359Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip has a photodetector region arranged within a semiconductor substrate. One or more dielectric materials are disposed within a trench defined by one or more interior surfaces of the semiconductor substrate. A doped epitaxial material is arranged within the trench and is laterally between the one or more dielectric materials and the photodetector region. A dielectric protection layer is arranged over the one or more dielectric materials within the trench. The dielectric protection layer laterally contacts a sidewall of the doped epitaxial material.Type: GrantFiled: March 11, 2020Date of Patent: May 4, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yueh-Chuan Lee, Chia-Chan Chen
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Patent number: 10998360Abstract: The present disclosure relates to a method of forming an integrated chip. The method may be performed by selectively etching a substrate to define a trench. One or more dielectric materials are formed within the trench. A part of the one or more dielectric materials are removed from within the trench to expose a sidewall of the substrate defining the trench. A doped epitaxial material is formed along the sidewall of the substrate.Type: GrantFiled: April 28, 2020Date of Patent: May 4, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yueh-Chuan Lee, Chia-Chan Chen
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Patent number: 10879123Abstract: A method for forming an integrated circuit (IC) package is provided. In some embodiments, a semiconductor workpiece comprising a scribe line, a first IC die, a second IC die, and a passivation layer is formed. The scribe line separates the first and second IC dies, and the passivation layer covers the first and second IC dies. The first IC die comprises a circuit and a pad structure electrically coupled to the circuit. The pad structure comprises a first pad, a second pad, and a bridge. The bridge is within the scribe line and connects the first pad to the second pad. The passivation layer is patterned to expose the first pad, but not the second pad, and testing is performed on the circuit through the first pad. The semiconductor workpiece is cut along the scribe line to individualize the first and second IC dies, and to remove the bridge.Type: GrantFiled: November 6, 2019Date of Patent: December 29, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yueh-Chuan Lee, Chia-Chan Chen, Ching-Heng Liu
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Publication number: 20200357762Abstract: Some embodiments relate to a bond pad structure of an integrated circuit (IC). The bond structure includes a bond pad and an intervening metal layer positioned below the bond pad. The intervening metal layer has a first face and a second face. A first via layer is in contact with the first face of intervening metal layer. The first via layer has a first via pattern including a single via. The bond structure also includes a second via layer in contact with the second face of the intervening metal layer. The second via layer has a second via pattern that is different than first via pattern. The second via pattern includes a first via surrounding a second via. The first and second vias are concentric with one another about a central point of the second via layer.Type: ApplicationFiled: July 29, 2020Publication date: November 12, 2020Inventors: Chia-Chan Chen, Yueh-Chuan Lee
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Publication number: 20200258925Abstract: The present disclosure relates to a method of forming an integrated chip. The method may be performed by selectively etching a substrate to define a trench. One or more dielectric materials are formed within the trench. A part of the one or more dielectric materials are removed from within the trench to expose a sidewall of the substrate defining the trench. A doped epitaxial material is formed along the sidewall of the substrate.Type: ApplicationFiled: April 28, 2020Publication date: August 13, 2020Inventors: Yueh-Chuan Lee, Chia-Chan Chen
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Patent number: 10734339Abstract: Some embodiments relate to a bond pad structure of an integrated circuit (IC). The bond structure includes a bond pad and an intervening metal layer positioned below the bond pad. The intervening metal layer has a first face and a second face. A first via layer is in contact with the first face of intervening metal layer. The first via layer has a first via pattern. The bond structure also includes a second via layer in contact with the second face of the intervening metal layer. The second via layer has a second via pattern that is different than first via pattern. The second via pattern includes a first group of elongated vias extending in parallel with one another in a first direction and a second group of vias in between the first group of elongated vias. The second group of vias extend in a second direction orthogonal to the first direction.Type: GrantFiled: March 21, 2019Date of Patent: August 4, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Chan Chen, Yueh-Chuan Lee
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Patent number: 10714516Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes doping a substrate to form a first well region having a first doping type, and selectively etching an upper surface of the substrate to define a trench extending into the first well region. The trench is filled with one or more dielectric materials. The substrate is implanted to form a first photodiode region within the substrate. The first photodiode region is separated from the trench by the first well region. A first part of the one or more dielectric materials is removed from within the trench to expose a sidewall of the substrate that defines the trench and that is proximate to the first photodiode region. A doped epitaxial material having the first doping type is formed along the sidewall of the substrate.Type: GrantFiled: September 22, 2019Date of Patent: July 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yueh-Chuan Lee, Chia-Chan Chen
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Publication number: 20200212093Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip has a photodetector region arranged within a semiconductor substrate. One or more dielectric materials are disposed within a trench defined by one or more interior surfaces of the semiconductor substrate. A doped epitaxial material is arranged within the trench and is laterally between the one or more dielectric materials and the photodetector region. A dielectric protection layer is arranged over the one or more dielectric materials within the trench. The dielectric protection layer laterally contacts a sidewall of the doped epitaxial material.Type: ApplicationFiled: March 11, 2020Publication date: July 2, 2020Inventors: Yueh-Chuan Lee, Chia-Chan Chen
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Patent number: 10672810Abstract: In some embodiments, the present disclosure relates to an integrated chip having a photodetector arranged within a semiconductor substrate having a first doping type. One or more dielectric materials are disposed within a trench defined by interior surfaces of the semiconductor substrate. A doped epitaxial material arranged within the trench at a location laterally between the one or more dielectric materials and the photodetector. The doped epitaxial material has a second doping type that is different than the first doping type.Type: GrantFiled: March 26, 2018Date of Patent: June 2, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yueh-Chuan Lee, Chia-Chan Chen
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Publication number: 20200111820Abstract: A photosensor device and the method of making the same are provided. In one embodiment, the device includes at least one pixel cell. The at least one pixel cell includes a substrate formed from a semiconductor material, and includes first and second photosensor regions. The first photosensor region is disposed in the substrate and includes a first dopant of a first conductivity type. The second photosensor region is disposed above the first photosensor region and includes a second dopant of a second conductivity type. The second photosensor region can have an increase in dopant concentration from an outer edge to a center portion therein.Type: ApplicationFiled: December 5, 2019Publication date: April 9, 2020Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Chan CHEN, Yueh-Chuan LEE, Ta-Hsin CHEN CHIEN, Shih-Hsien HUANG, Chih-Huang LI
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Publication number: 20200105610Abstract: A semiconductor arrangement is provided. The semiconductor arrangement includes a first conductive element over a substrate and a second conductive element over the substrate. A dielectric region is over a top surface of the substrate and between the first conductive element and the second conductive element. An electrically conductive structure is over the first conductive element, the second conductive element, and the dielectric region.Type: ApplicationFiled: September 20, 2019Publication date: April 2, 2020Inventors: Yueh-Chuan Lee, Chia-Chan Chen
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Publication number: 20200075416Abstract: A method for forming an integrated circuit (IC) package is provided. In some embodiments, a semiconductor workpiece comprising a scribe line, a first IC die, a second IC die, and a passivation layer is formed. The scribe line separates the first and second IC dies, and the passivation layer covers the first and second IC dies. The first IC die comprises a circuit and a pad structure electrically coupled to the circuit. The pad structure comprises a first pad, a second pad, and a bridge. The bridge is within the scribe line and connects the first pad to the second pad. The passivation layer is patterned to expose the first pad, but not the second pad, and testing is performed on the circuit through the first pad. The semiconductor workpiece is cut along the scribe line to individualize the first and second IC dies, and to remove the bridge.Type: ApplicationFiled: November 6, 2019Publication date: March 5, 2020Inventors: Yueh-Chuan Lee, Chia-Chan Chen, Ching-Heng Liu
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Publication number: 20200020727Abstract: In some embodiments, the present disclosure relates to a method of forming an integrated chip. The method includes doping a substrate to form a first well region having a first doping type, and selectively etching an upper surface of the substrate to define a trench extending into the first well region. The trench is filled with one or more dielectric materials. The substrate is implanted to form a first photodiode region within the substrate. The first photodiode region is separated from the trench by the first well region. A first part of the one or more dielectric materials is removed from within the trench to expose a sidewall of the substrate that defines the trench and that is proximate to the first photodiode region. A doped epitaxial material having the first doping type is formed along the sidewall of the substrate.Type: ApplicationFiled: September 22, 2019Publication date: January 16, 2020Inventors: Yueh-Chuan Lee, Chia-Chan Chen
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Patent number: 10515989Abstract: A photosensor device and the method of making the same are provided. In one embodiment, the device includes at least one pixel cell. The at least one pixel cell includes a substrate formed from a semiconductor material, and includes first and second photosensor regions. The first photosensor region is disposed in the substrate and includes a first dopant of a first conductivity type. The second photosensor region is disposed above the first photosensor region and includes a second dopant of a second conductivity type. The second photosensor region can have an increase in dopant concentration from an outer edge to a center portion therein.Type: GrantFiled: August 30, 2017Date of Patent: December 24, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Chan Chen, Yueh-Chuan Lee, Ta-Hsin Chen, Shih-Hsien Huang, Chih-Huang Li
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Patent number: 10510606Abstract: A method for forming an integrated circuit (IC) package is provided. In some embodiments, a semiconductor workpiece comprising a scribe line, a first IC die, a second IC die, and a passivation layer is formed. The scribe line separates the first and second IC dies, and the passivation layer covers the first and second IC dies. The first IC die comprises a circuit and a pad structure electrically coupled to the circuit. The pad structure comprises a first pad, a second pad, and a bridge. The bridge is within the scribe line and connects the first pad to the second pad. The passivation layer is patterned to expose the first pad, but not the second pad, and testing is performed on the circuit through the first pad. The semiconductor workpiece is cut along the scribe line to individualize the first and second IC dies, and to remove the bridge.Type: GrantFiled: April 26, 2019Date of Patent: December 17, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yueh-Chuan Lee, Chia-Chan Chen, Ching-Heng Liu