Abstract: A method for forming an integrated circuit (IC) package is provided. In some embodiments, a semiconductor workpiece comprising a scribe line, a first IC die, a second IC die, and a passivation layer is formed. The scribe line separates the first and second IC dies, and the passivation layer covers the first and second IC dies. The first IC die comprises a circuit and a pad structure electrically coupled to the circuit. The pad structure comprises a first pad, a second pad, and a bridge. The bridge is within the scribe line and connects the first pad to the second pad. The passivation layer is patterned to expose the first pad, but not the second pad, and testing is performed on the circuit through the first pad. The semiconductor workpiece is cut along the scribe line to individualize the first and second IC dies, and to remove the bridge.

Abstract: Some embodiments relate to a bond pad structure of an integrated circuit (IC). The bond structure includes a bond pad and an intervening metal layer positioned below the bond pad. The intervening metal layer has a first face and a second face. A first via layer is in contact with the first face of intervening metal layer. The first via layer has a first via pattern. The bond structure also includes a second via layer in contact with the second face of the intervening metal layer. The second via layer has a second via pattern that is different than first via pattern. The second via pattern includes a first group of elongated vias extending in parallel with one another in a first direction and a second group of vias in between the first group of elongated vias. The second group of vias extend in a second direction orthogonal to the first direction.

Abstract: In some embodiments, the present disclosure relates to an integrated chip having a photodetector arranged within a semiconductor substrate having a first doping type. One or more dielectric materials are disposed within a trench defined by interior surfaces of the semiconductor substrate. A doped epitaxial material arranged within the trench at a location laterally between the one or more dielectric materials and the photodetector. The doped epitaxial material has a second doping type that is different than the first doping type.

Abstract: Some embodiments relate to a bond pad structure of an integrated circuit (IC). In one embodiment the bond structure includes a bond pad and an intervening metal layer positioned below the bond pad. The intervening metal layer has a first face and a second face. A first via layer is in contact with the first face of intervening metal layer. The first via layer has a first via pattern. The bond structure also includes a second via layer in contact with the second face of the intervening metal layer. The second via layer has a second via pattern that is different than first via pattern.

Abstract: A method for forming an integrated circuit (IC) package is provided. In some embodiments, a semiconductor workpiece comprising a scribe line, a first IC die, a second IC die, and a passivation layer is formed. The scribe line separates the first and second IC dies, and the passivation layer covers the first and second IC dies. The first IC die comprises a circuit and a pad structure electrically coupled to the circuit. The pad structure comprises a first pad, a second pad, and a bridge. The bridge is within the scribe line and connects the first pad to the second pad. The passivation layer is patterned to expose the first pad, but not the second pad, and testing is performed on the circuit through the first pad. The semiconductor workpiece is cut along the scribe line to individualize the first and second IC dies, and to remove the bridge.

Abstract: A photosensor device and the method of making the same are provided. In one embodiment, the device includes at least one pixel cell. The at least one pixel cell includes a substrate formed from a semiconductor material, and includes first and second photosensor regions. The first photosensor region is disposed in the substrate and includes a first dopant of a first conductivity type. The second photosensor region is disposed above the first photosensor region and includes a second dopant of a second conductivity type. The second photosensor region can have an increase in dopant concentration from an outer edge to a center portion therein.

Abstract: A method for forming an integrated circuit (IC) package is provided. In some embodiments, a semiconductor workpiece comprising a scribe line, a first IC die, a second IC die, and a passivation layer is formed. The scribe line separates the first and second IC dies, and the passivation layer covers the first and second IC dies. The first IC die comprises a circuit and a pad structure electrically coupled to the circuit. The pad structure comprises a first pad, a second pad, and a bridge. The bridge is within the scribe line and connects the first pad to the second pad. The passivation layer is patterned to expose the first pad, but not the second pad, and testing is performed on the circuit through the first pad. The semiconductor workpiece is cut along the scribe line to individualize the first and second IC dies, and to remove the bridge.

Abstract: A method for forming an image sensor device on a substrate is disclosed. The method includes (a) recessing a portion of the substrate thereby forming a first shallow trench; (b) forming a spacer layer surrounding at least part of a sidewall of the first shallow trench; and (c) forming a first deep trench that extends below the first shallow trench by further recessing the substrate while using the spacer layer as a mask.

Abstract: A method for forming a backside illuminated (BSI) image sensor device structure is provided. The BSI image sensor includes a first substrate having a top surface and a bottom surface, and a plurality of pixel regions formed at the top surface of the first substrate. The BSI image sensor also includes a grid structure through the first substrate and between two adjacent pixel regions. The grid structure extends continuously through the first substrate in a vertical direction and has a top surface and a bottom surface, the top surface of the grid structure protrudes above the bottom surface of the first substrate, and the bottom surface is leveled with the top surface of the first substrate.

Abstract: A method for forming an image sensor device on a substrate is disclosed. The method includes (a) recessing a portion of the substrate thereby forming a first shallow trench; (b) forming a spacer layer surrounding at least part of a sidewall of the first shallow trench; and (c) forming a first deep trench that extends below the first shallow trench by further recessing the substrate while using the spacer layer as a mask.

Abstract: The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding from the sidewalls respectively. The bonding pads are disposed on the protruding portions respectively. The wafer dicing method includes following operations. Chips are formed on a semiconductor wafer. Bonding pads are formed at a border line between every two of the adjacent chips. A scribe line is formed and disposed along the bonding pads. A photolithographic pattern is formed on a top layer of the semiconductor wafer to expose the scribe line. The scribe line is etched to a depth in the semiconductor wafer substantially below the top layer to form an etched pattern. A back surface of the semiconductor wafer is thinned until the etched pattern in the semiconductor wafer is exposed.

Abstract: A method for forming a backside illuminated (BSI) image sensor device structure is provided. The BSI image sensor includes a first substrate having a top surface and a bottom surface, and a plurality of pixel regions formed at the top surface of the first substrate. The BSI image sensor also includes a grid structure through the first substrate and between two adjacent pixel regions. The grid structure extends continuously through the first substrate in a vertical direction and has a top surface and a bottom surface, the top surface of the grid structure protrudes above the bottom surface of the first substrate, and the bottom surface is leveled with the top surface of the first substrate.

Abstract: A complementary metal-oxide-semiconductor (CMOS) image sensor with silicon and silicon germanium is provided. A silicon germanium layer abuts a silicon layer. A photodetector is arranged in the silicon germanium layer. A transistor is arranged on the silicon layer with a source/drain region that is buried in a surface of the silicon layer and that is electrically coupled to the photodetector. A method for manufacturing the CMOS image sensor is also provided.

Abstract: Some embodiments relate to a bond pad structure of an integrated circuit (IC). In one embodiment the bond structure includes a bond pad and an intervening metal layer positioned below the bond pad. The intervening metal layer has a first face and a second face. A first via layer is in contact with the first face of intervening metal layer. The first via layer has a first via pattern. The bond structure also includes a second via layer in contact with the second face of the intervening metal layer. The second via layer has a second via pattern that is different than first via pattern.

Abstract: The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding from the sidewalls respectively. The bonding pads are disposed on the protruding portions respectively. The wafer dicing method includes following operations. Chips are formed on a semiconductor wafer. Bonding pads are formed at a border line between every two of the adjacent chips. A scribe line is formed and disposed along the bonding pads. A photolithographic pattern is formed on a top layer of the semiconductor wafer to expose the scribe line. The scribe line is etched to a depth in the semiconductor wafer substantially below the top layer to form an etched pattern. A back surface of the semiconductor wafer is thinned until the etched pattern in the semiconductor wafer is exposed.

Abstract: A backside illuminated (BSI) image sensor with a reflector is provided. A pixel sensor is arranged on a lower side of a semiconductor substrate, and comprises a photodetector arranged within the semiconductor substrate. An interconnect structure is arranged under the semiconductor substrate and the pixel sensor, and comprises an interconnect layer and a contact via extending from the interconnect layer to the pixel sensor. The reflector is arranged under the photodetector, between the interconnect layer and the photodetector, and is configured to reflect incident radiation towards the photodetector. A method for manufacturing the BSI image sensor is also provided.

Abstract: The semiconductor die includes a base body, protruding portions and bonding pads. The base body has sidewalls. The protruding portions are laterally protruding from the sidewalls respectively. The bonding pads are disposed on the protruding portions respectively. The wafer dicing method includes following operations. Chips are formed on a semiconductor wafer. Bonding pads are formed on a border line between every two of the adjacent chips. A scribe line is formed and disposed along the bonding pads. A photolithographic pattern is formed on a top surface of the semiconductor wafer to expose the scribe line. The scribe line is etched to a depth in the semiconductor wafer substantially below the top surface layer to form an etched pattern. A back surface of the semiconductor wafer is thinned until the etched pattern in the wafer substrate is exposed.

Abstract: Test line structures on a wafer are provided. A first testing pad is formed in a scribe line of the wafer. A second testing pad is formed in the scribe line. A transistor under test is formed in the scribe line and is coupled between the first testing pad and the second testing pad. A device is formed in the scribe line and is coupled between the first testing pad and the transistor under test. A third testing pad is formed in the scribe line and is coupled between the device and the transistor under test. A current passing through the transistor under test is measured via the second testing pad or the first testing pad when a first voltage is applied to the first testing pad, wherein the first voltage is determined according to a second voltage from the third testing pad.

Abstract: A backside illuminated (BSI) image sensor with a reflector is provided. A pixel sensor is arranged on a lower side of a semiconductor substrate, and comprises a photodetector arranged within the semiconductor substrate. An interconnect structure is arranged under the semiconductor substrate and the pixel sensor, and comprises an interconnect layer and a contact via extending from the interconnect layer to the pixel sensor. The reflector is arranged under the photodetector, between the interconnect layer and the photodetector, and is configured to reflect incident radiation towards the photodetector. A method for manufacturing the BSI image sensor is also provided.

Abstract: A complementary metal-oxide-semiconductor (CMOS) image sensor with silicon and silicon germanium is provided. A silicon germanium layer abuts a silicon layer. A photodetector is arranged in the silicon germanium layer. A transistor is arranged on the silicon layer with a source/drain region that is buried in a surface of the silicon layer and that is electrically coupled to the photodetector. A method for manufacturing the CMOS image sensor is also provided.