Abstract: A DC brushless motor operation speed control method is disclosed. First, a linearly voltage dependent current source is used to charge a capacitor and the terminal voltage of the capacitor is coupled to a linearly voltage dependent base frequency level detector. When the output voltage of the capacitor reaches the base frequency reference voltage, the signal output from the base frequency level detector will make the capacitor discharge, outputting a series of base frequency triangular waves. Under different supply voltages, all the generated base frequency triangular waves have the same cycle time. The base frequency triangular waves are transmitted to a speed control comparator. Through pulse width modulation, the speed control reference voltage adjusts the output pulse width of the comparator and thereby controls the speed of the motor.

Abstract: A power source protecting device comprises a power source switching unit for shutting off the power supply from an AC power source according to an open control signal, a surge voltage protecting unit for outputting the open control signal when a surge voltage occurs, a leakage current protecting unit for outputting the open control signal when a leakage current occurs, and an over-current protecting unit for outputting the open control signal according to a current value when an over-current occurs. The present invention can provides the surge voltage protection, the leakage current protection and the over current protection at the same time. In comparison with the conventional power source protecting device, the invention can provide a more compact and low cost device, and is able to provide an accurate and safe protection according to the current detection based on an energy.

Abstract: An input apparatus and method for use in an information input unit. The information input unit is coupled to an information device having a display. The input apparatus includes an operational selection module, which is coupled to the information input unit, for generating a press signal in response to a pressing operation detected by the operational selection module and for generating a shift signal in response to a shifting operation detected by the operational selection module. A control chip of the information input unit activates the information device to display a graphical interface indicative of a set of options on the display when the information input unit receives the shift signal. Selection of the set of options on the graphical interface is made according to the press signal and the shift signal.

Abstract: A method for driving a brushless DC motor is disclosed in accordance with the present invention. Firstly, a driving control signal is generated based on sensed information of a motor rotor's magnetic field distribution. The driving control signal is inactive in the case that four rotor magnetic arcs are rotated more or less than critical positions of the rotor corresponding a stator. At that time, no magnetic fields are produced from the motor's stator, and thus the rotor rotates by inertial force. In another case, the driving control signal is issued in a conventional manner.

Abstract: A method for driving a brushless DC motor is disclosed in accordance with the present invention. Firstly, a driving control signal is generated based on sensed information of a motor rotor's magnetic field distribution. The driving control signal is inactive in the case that four rotor magnetic arcs are rotated more or less than critical positions of the rotor corresponding a stator. At that time, no magnetic fields are produced from the motor's stator, and thus the rotor rotates by inertial force. In another case, the driving control signal is issued in a conventional manner.

Abstract: A system for controlling the rotational speed of a fan, according to a reference clock having a reference frequency, is disclosed. The rotational speed corresponds to a fan rotational speed signal. The fan rotational speed controlling unit compares the reference clock with the fan rotational speed signal, to output a speed controlling signal. The voltage generating circuit generates a level signal corresponding to the speed controlling signal. The driving unit generates a driving signal to control the rotational speed of the fan according to the level signal. When the fan is assembled with the controlling system, only coils with the same turns need to be use to obtain various rated rotational speeds of fans of different specifications by altering the reference frequency of the controlling system. Because coils with different turns are not required in stock at the same time, the time cost and the manufacturing cost can be reduced.

Abstract: A DC brushless motor operation speed control method is disclosed. First, a linearly voltage dependent current source is used to charge a capacitor and the terminal voltage of the capacitor is coupled to a linearly voltage dependent base frequency level detector. When the output voltage of the capacitor reaches the base frequency reference voltage, the signal output from the base frequency level detector will make the capacitor discharge, outputting a series of base frequency triangular waves. Under different supply voltages, all the generated base frequency triangular waves have the same cycle time. The base frequency triangular waves are transmitted to a speed control comparator. Through pulse width modulation, the speed control reference voltage adjusts the output pulse width of the comparator and thereby controls the speed of the motor.

Abstract: A processor architecture is disclosed including a fetcher, packet unit and branch target buffer. The branch target buffer is provided with a tag RAM that is organized in a set associative fashion. In response to receiving a search address, multiple sets in the tag RAM are simultaneously searched for a branch instruction that is predicted to be taken. The packet unit has a queue into which fetched cache blocks are stored containing instructions. Sequentially fetched cache blocks are stored in adjacent locations of the queue. The queue entries also have indicators that indicate whether or not a starting or final data word of an instruction sequence is contained in the queue entry and if so, an offset indicating the particular starting or final data word. In response, the packet unit concatenates data words of an instruction sequence into contiguous blocks. The fetcher generates a fetch address for fetching a cache block from the instruction cache containing instructions to be executed.

Abstract: A processor architecture is disclosed including a fetcher, packet unit and branch target buffer. The branch target buffer is provided with a tag RAM that is organized in a set associative fashion. In response to receiving a search address, multiple sets in the tag RAM are simultaneously searched for a branch instruction that is predicted to be taken. The packet unit has a queue into which fetched cache blocks are stored containing instructions. Sequentially fetched cache blocks are stored in adjacent locations of the queue. The queue entries also have indicators that indicate whether or not a starting or final data word of an instruction sequence is contained in the queue entry and if so, an offset indicating the particular starting or final data word. In response, the packet unit concatenates data words of an instruction sequence into contiguous blocks. The fetcher generates a fetch address for fetching a cache block from the instruction cache containing instructions to be executed.

Abstract: A data processing system for decoding instructions in parallel in a superscalar, complex instruction set computing (CISC) computer. In a training mode of operation, an encrypter 29 encrypts preprocessed instructions retrieved from an instruction cache 26. In a processing mode of operation, instruction information is fetched and decrypted in decrypter 30. A prefetcher 21 separates the fetched instruction according to the decrypted boundary information. An instruction length verifier 25 verifies that the instructions were separated correctly and controls decoders 22a-c according to the verification. If the verification is correct for a given set of instructions, the system processes the instructions in parallel through the decoders to a dispatch logic circuit 23 and then to functional units 24. If the verification is incorrect, those related instructions may be needed to decode serially.