Abstract: A test key structure for use in measuring step height includes a substrate, and a pair of test contacts. The substrate includes an isolation region and a diffusion region. The test contact pair includes a first test contact and a second test contact for measuring electrical resistances. The first test contact is disposed on the diffusion region and the second test contact is disposed on the isolation region.

Abstract: A layout method of a semiconductor circuit is provided. The layout method is firstly putting a plurality of circuit patterns on a substrate, wherein a first distance is the largest distance between any one of the circuit patterns and one of other circuit patterns adjacent thereto. The layout method is then determining whether the first distance is larger than a first critical value. Later, when the first distance is larger than the first critical value, at least a closed loop dummy pattern is putted in one of the areas corresponding to the first distance between the pair of the circuit patterns. The closed loop dummy pattern is putted in a same layer with the circuit patterns, surrounds between the pair of circuit patterns and is insulated from the circuit patterns.

Abstract: A layout method of a semiconductor circuit is provided. The layout method is firstly putting a plurality of circuit patterns on a substrate, wherein a first distance is the largest distance between any one of the circuit patterns and one of other circuit patterns adjacent thereto. The layout method is then determining whether the first distance is larger than a first critical value. Later, when the first distance is larger than the first critical value, at least a closed loop dummy pattern is putted in one of the areas corresponding to the first distance between the pair of the circuit patterns. The closed loop dummy pattern is putted in a same layer with the circuit patterns, surrounds between the pair of circuit patterns and is insulated from the circuit patterns.

Abstract: A semiconductor circuit structure includes a substrate and an interconnect structure. The interconnect structure is disposed on the substrate and includes a plurality of circuit patterns and at least one closed loop pattern. The closed loop pattern is in a same layer with the circuit patterns, surrounds between the circuit patterns and is insulated from the circuit patterns. The closed loop pattern can protect the circuit patterns from being damaged by stresses, for improving a mechanical strength of the semiconductor circuit structure.

Abstract: The present invention provides a structure of a resistor comprising: a substrate having an interfacial layer thereon; a resistor trench formed in the interfacial layer; at least a work function metal layer covering the surface of the resistor trench; at least two metal bulks located at two ends of the resistor trench and adjacent to the work function metal layer; and a filler formed between the two metal bulks inside the resistor trench, wherein the metal bulks are direct in contact with the filler.

Abstract: A test key structure for use in measuring step height includes a substrate, and a pair of test contacts. The substrate includes an isolation region and a diffusion region. The test contact pair includes a first test contact and a second test contact for measuring electrical resistances. The first test contact is disposed on the diffusion region and the second test contact is disposed on the isolation region.

Abstract: A method for inspecting a photoresist pattern is disclosed. First, a substrate with a first doping region is provided. Then, a photoresist is formed to cover the substrate. Later, the photoresist is patterned to form a photoresist pattern. Afterwards, the substrate is doped by using the photoresist pattern, and a PN junction exists in the first doping region. Thereafter, a current passing through the PN junction is tested to inspect the photoresist pattern.

Abstract: A semiconductor circuit structure includes a substrate and an interconnect structure. The interconnect structure is disposed on the substrate and includes a plurality of circuit patterns and at least one closed loop pattern. The closed loop pattern is in a same layer with the circuit patterns, surrounds between the circuit patterns and is insulated from the circuit patterns. The closed loop pattern can protect the circuit patterns from being damaged by stresses, for improving a mechanical strength of the semiconductor circuit structure.

Abstract: A method for inspecting a photoresist pattern is disclosed. First, a substrate with a first doping region is provided. Then, a photoresist is formed to cover the substrate. Later, the photoresist is patterned to form a photoresist pattern. Afterwards, the substrate is doped by using the photoresist pattern, and a PN junction exists in the first doping region. Thereafter, a current passing through the PN junction is tested to inspect the photoresist pattern.