Patents by Inventor Chia-Chen Wu

Chia-Chen Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190369920
    Abstract: A resistive memory including a storage array, a storage circuit, a control circuit, a voltage generation circuit and an access circuit is provided. The storage array includes a plurality of blocks. Each block includes a plurality of memory cells. The storage circuit stores a plurality of count values. Each of the count values indicates the number of times that a corresponding block performs a write operation. The control circuit generates a control signal according to the count values when an external command is a write command. The voltage generation circuit provides an operation voltage group according to the control signal. The access circuit accesses the storage array according to the operation voltage group.
    Type: Application
    Filed: March 14, 2019
    Publication date: December 5, 2019
    Inventors: Ping-Kun WANG, Shao-Ching LIAO, Chien-Min WU, Chia Hua HO, Frederick CHEN, He-Hsuan CHAO, Seow-Fong LIM
  • Patent number: 10498481
    Abstract: A method of new radio physical broadcast channel (NR-PBCH) bit mapping is proposed to improve for NR-PBCH decoding performance under Polar codes. NR-PBCH carries 32 information bits and 24 CRC bits. Specifically, NR-PBCH uses 512-bit Polar codes to carry total 56 data bits. Different Polar code bit channels have different channel reliability. As a general rule, the most reliable Polar code bit channels are used for the 56 data bits. In accordance with a novel aspect, within the 32 NR-PBCH information bits, some of the information bits that can be known to the decoders under certain conditions and therefore are placed at the least reliable Polar code bit positions. As a result, by mapping the NR-PBCH data bits properly at the input bit positions of Polar codes, the NR-PBCH decoding performance is improved when the known bits a priori can be exploited.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: December 3, 2019
    Assignee: MEDIATEK INC.
    Inventors: Wei-De Wu, Chia-Wei Tai, Tao Chen, Yen-Cheng Liu, Xiu-Sheng Li, Wei-Jen Chen
  • Patent number: 10483159
    Abstract: The present disclosure describes methods which employ a patterning photolithography/etch operations to form self-aligned interconnects with multi-metal gap fill. For example, the method includes a first pattern structure and a second pattern structure formed over a dielectric layer. Each of the first and second pattern structures includes a pair of spacers, and a center portion between the pair of spacers. A first opening, self-aligned to a space between the first and second pattern structures, is formed in the dielectric layer. A first conductive material is deposited in the first opening. The center portion of the second pattern structure is removed to form a void above the dielectric layer and between the pair of spacers of the second pattern structure. A second opening, self-aligned to the void, is formed in the dielectric layer; and a second conductive material is deposited in the second opening.
    Type: Grant
    Filed: June 15, 2018
    Date of Patent: November 19, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Wei-Chen Chu, Tai-I Yang, Cheng-Chi Chuang, Chia-Tien Wu
  • Patent number: 10454112
    Abstract: An anode and a lithium ion battery employing the same are provided. The anode includes a lithium-containing layer and a single-ion conductive layer. The single-ion conductive layer includes an inorganic particle, a single-ion conductor polymer, and a binder. The single-ion conductor polymer has a first repeat unit of Formula (I), a second repeat unit of Formula (II), a third repeat unit of Formula (III), and a fourth repeat unit of Formula (IV) wherein R1 is O?M+, SO3?M+, N(SO2F)?M+, N(SO2CF3)?M+, N(SO2CF2CF3)?M+, COO?M+, or PO4?M+; M+ is Li+, Na+, K+, Cs+, or a combination thereof; and R2 is CH3, CH2CH3, or CH2CH2OCH2CH3. In particular, the weight ratio of the inorganic particle to the sum of the single-ion conductor polymer and the binder is from 4:1 to 9:1, and the weight ratio of the binder to the single-ion conductor polymer is from 1:1 to 9:1.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: October 22, 2019
    Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Wei-Hsin Wu, Sheng-Hui Wu, Chi-Yang Chao, Kun-Lin Liu, Chia-Chen Fang
  • Publication number: 20190244902
    Abstract: A first metal layer of a semiconductor device includes a plurality of first metal lines that each extend along a first axis, and a first rail structure that extends along the first axis. The first rail structure is physically separated from the first metal lines. A second metal layer is located over the first metal layer. The second metal layer includes a plurality of second metal lines that each extend along a second axis orthogonal to the first axis, and a second rail structure that extends along the first axis. The second rail structure is physically separated from the second metal lines. The second rail structure is located directly over the first rail structure. A plurality of vias is located between the first metal layer and the second metal layer. A subset of the vias electrically interconnects the first rail structure to the second rail structure.
    Type: Application
    Filed: April 15, 2019
    Publication date: August 8, 2019
    Inventors: Chia-Tien Wu, Hsiang-Wei Liu, Wei-Chen Chu
  • Publication number: 20190207222
    Abstract: An anode and a lithium ion battery employing the same are provided. The anode includes a lithium-containing layer and a single-ion conductive layer. The single-ion conductive layer includes an inorganic particle, a single-ion conductor polymer, and a binder. The single-ion conductor polymer has a first repeat unit of Formula (I), a second repeat unit of Formula (II), a third repeat unit of Formula (III), and a fourth repeat unit of Formula (IV) wherein R1 is O?M+, SO3?M?, N(SO2F)?M+, N(SO2CF3)?M+, N(SO2CF2CF3)?M+, COO?M+, or PO4?M+; M+ is Li+, Na+, K+, Cs+, or a combination thereof; and R2 is CH3, CH2CH3, or CH2CH2OCH2CH3. In particular, the weight ratio of the inorganic particle to the sum of the single-ion conductor polymer and the binder is from 4:1 to 9:1, and the weight ratio of the binder to the single-ion conductor polymer is from 1:1 to 9:1.
    Type: Application
    Filed: December 29, 2017
    Publication date: July 4, 2019
    Applicant: Industrial Technology Research Institute
    Inventors: Wei-Hsin WU, Sheng-Hui WU, Chi-Yang CHAO, Kun-Lin LIU, Chia-Chen FANG
  • Patent number: 10332889
    Abstract: A method of manufacturing a semiconductor device is provided, which includes the steps of providing a capacitor structure, forming a conductive layer on the capacitor structure, performing a hydrogen doping process to the conductive layer, forming a metal layer on the conductive layer after the hydrogen doping process, and patterning the metal layer and the conductive layer to forma top electrode plate.
    Type: Grant
    Filed: April 12, 2018
    Date of Patent: June 25, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Ger-Pin Lin, Tien-Chen Chan, Shu-Yen Chan, Chi-Mao Hsu, Shih-Fang Tzou, Ting-Pang Chung, Chia-Wei Wu
  • Publication number: 20190168475
    Abstract: A sole assembly may be formed by a method that includes positioning a plurality of preforms having different colors together to form a sole assembly preform and placing the sole assembly preform in a recess in a first portion of a mold assembly. The sole assembly preform is subjected to heat for a predetermined amount of time such that the plurality of preforms bond to one another to form a sole assembly.
    Type: Application
    Filed: January 29, 2019
    Publication date: June 6, 2019
    Inventors: Tee L. Wan, Thienchai Chaisumrej, Chia-Yi Wu, Yu-Chen Lin
  • Publication number: 20190161346
    Abstract: The present disclosure relates to a micro-electro mechanical system (MEMS) package and a method of achieving differential pressure adjustment in multiple MEMS cavities at a wafer-to-wafer bonding level. A device substrate comprising first and second MEMS devices is bonded to a capping substrate comprising first and second recessed regions. A ventilation trench is laterally spaced apart from the recessed regions and within the second cavity. A sealing structure is arranged within the ventilation trench and defines a vent in fluid communication with the second cavity. A cap is arranged within the vent to seal the second cavity at a second gas pressure that is different than a first gas pressure of the first cavity.
    Type: Application
    Filed: November 28, 2017
    Publication date: May 30, 2019
    Inventors: Yi-Chia Lee, Chin-Min Lin, Cheng San Chou, Hsiang-Fu Chen, Wen-Chuan Tai, Ching-Kai Shen, Hua-Shu Ivan Wu, Fan Hu
  • Publication number: 20190138354
    Abstract: The present invention provides a method for scheduling jobs with idle resources. When the computational units of computers are idle, according to the variation of idle time, appropriate jobs may be allocated to the computational units. Then the unscheduled jobs may be completed by using idle time segments. Thereby, the utilization rate of computation resources and the completion rate of jobs may be enhanced.
    Type: Application
    Filed: November 5, 2018
    Publication date: May 9, 2019
    Inventors: CHIA-CHEN KUO, I-CHEN WU, LUNG-PIN CHEN, CHUAN-LIN LAI, YEN-LING CHANG, CHENG-LUN TSAI, CHIANG-HSIANG LIEN
  • Patent number: 10276389
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a silicon layer on a substrate; forming a first metal silicon nitride layer on the silicon layer; performing an oxygen treatment process to form an oxide layer on the first metal silicon nitride layer; forming a second metal silicon nitride layer on the oxide layer; forming a conductive layer on the second metal silicon nitride layer; and patterning the conductive layer, the second metal silicon nitride layer, the oxide layer, the first metal silicon nitride layer, and the silicon layer to form a gate structure.
    Type: Grant
    Filed: May 23, 2018
    Date of Patent: April 30, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chih-Chieh Tsai, Yi-Wei Chen, Pin-Hong Chen, Chih-Chien Liu, Tzu-Chieh Chen, Chun-Chieh Chiu, Tsun-Min Cheng, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang
  • Publication number: 20190067296
    Abstract: A method for fabricating buried word line of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a first conductive layer in the trench; forming a second conductive layer on the first conductive layer, in which the second conductive layer above the substrate and the second conductive layer below the substrate comprise different thickness; and forming a third conductive layer on the second conductive layer to fill the trench.
    Type: Application
    Filed: September 22, 2017
    Publication date: February 28, 2019
    Inventors: Pin-Hong Chen, Yi-Wei Chen, Tzu-Chieh Chen, Chih-Chieh Tsai, Chia-Chen Wu, Kai-Jiun Chang, Yi-An Huang, Tsun-Min Cheng
  • Patent number: 10211211
    Abstract: A method for fabricating a buried word line (BWL) of a dynamic random access memory (DRAM) includes the steps of: forming a trench in a substrate; forming a barrier layer in the trench; performing a soaking process to reduce chlorine concentration in the barrier layer; and forming a conductive layer to fill the trench.
    Type: Grant
    Filed: December 4, 2017
    Date of Patent: February 19, 2019
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Kai-Jiun Chang, Yi-Wei Chen, Tsun-Min Cheng, Chia-Chen Wu, Pin-Hong Chen, Chih-Chieh Tsai, Tzu-Chieh Chen, Yi-An Huang
  • Publication number: 20190027479
    Abstract: A method of fabricating a cobalt silicide layer includes providing a substrate disposed in a chamber. A deposition process is performed to form a cobalt layer covering the substrate. The deposition process is performed when the temperature of the substrate is between 50° C. and 100° C., and the temperature of the chamber is between 300° C. and 350° C. After the deposition process, an annealing process is performed to transform the cobalt layer into a cobalt silicide layer. The annealing process is performed when the substrate is between 300° C. and 350° C., and the duration of the annealing process is between 50 seconds and 60 seconds.
    Type: Application
    Filed: May 29, 2018
    Publication date: January 24, 2019
    Inventors: Chia-Chen Wu, Yi-Wei Chen, Chi-Mao Hsu, Kai-Jiun Chang, Chih-Chieh Tsai, Pin-Hong Chen, Tsun-Min Cheng, Yi-An Huang
  • Publication number: 20190013320
    Abstract: A semiconductor memory device is provided, and which includes a substrate, plural gates, plural plugs, a capacitor structure and a conducting cap layer. The gates are disposed within the substrate, and the plugs are disposed on the substrate, with each plug electrically connected to two sides of each gate on the substrate. The capacitor structure is disposed on the substrate, and the capacitor structure includes plural capacitors, with each capacitor electrically connected to the plugs respectively. The conducting cap layer covers the top surface and sidewalls of the capacitor structure. Also, the semiconductor memory device further includes an adhesion layer and an insulating layer. The adhesion layer covers the conducting cap layer and the capacitor structure, and the insulating layer covers the adhesion layer.
    Type: Application
    Filed: May 22, 2018
    Publication date: January 10, 2019
    Inventors: Tzu-Chieh Chen, Pin-Hong Chen, Chih-Chieh Tsai, Chia-Chen Wu, Yi-An Huang, Kai-Jiun Chang, Tsun-Min Cheng, Yi-Wei Chen
  • Publication number: 20180350673
    Abstract: A method of forming a semiconductor structure includes providing a material layer having a recess formed therein. A first tungsten metal layer is formed at a first temperature and fills the recess. An anneal process at a second temperature is then performed, wherein the second temperature is higher than the first temperature.
    Type: Application
    Filed: March 21, 2018
    Publication date: December 6, 2018
    Inventors: Pin-Hong Chen, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Tsun-Min Cheng, Yi-Wei Chen, Wei-Hsin Liu
  • Publication number: 20180301458
    Abstract: The present invention provides a storage node contact structure of a memory device comprising a substrate having a dielectric layer comprising a recess, a first tungsten metal layer, and an adhesive layer on the first tungsten metal layer and a second tungsten metal layer on the adhesive layer, wherein the second tungsten metal layer is formed by a physical vapor deposition (PVD).
    Type: Application
    Filed: March 15, 2018
    Publication date: October 18, 2018
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen, Hsin-Fu Huang, Chi-Mao Hsu, Li-Wei Feng, Ying-Chiao Wang, Chung-Yen Feng
  • Publication number: 20180190662
    Abstract: A method of forming a bit line gate structure of a dynamic random access memory (DRAM) includes the following. A hard mask layer is formed on a metal stack by a chemical vapor deposition process importing nitrogen (N2) gases and then importing amonia (NH3) gases. The present invention also provides a bit line gate structure of a dynamic random access memory (DRAM) including a metal stack and a hard mask. The metal stack includes a polysilicon layer, a titanium layer, a titanium nitride layer, a first tungsten nitride layer, a tungsten layer and a second tungsten nitride layer stacked from bottom to top. The hard mask is disposed on the metal stack.
    Type: Application
    Filed: December 27, 2017
    Publication date: July 5, 2018
    Inventors: Tzu-Chin Wu, Wei-Hsin Liu, Yi-Wei Chen, Mei-Ling Chen, Chia-Lung Chang, Ching-Hsiang Chang, Jui-Min Lee, Tsun-Min Cheng, Lin-Chen Lu, Shih-Fang Tzou, Kai-Jiun Chang, Chih-Chieh Tsai, Tzu-Chieh Chen, Chia-Chen Wu
  • Patent number: 9953982
    Abstract: A method for fabricating semiconductor device includes the steps of: forming a shallow trench isolation (STI) in a substrate; removing part of the STI to form a first trench; forming a cap layer in the first trench; forming a mask layer on the cap layer and the substrate; and removing part of the mask layer, part of the cap layer, and part of the STI to form a second trench.
    Type: Grant
    Filed: March 23, 2017
    Date of Patent: April 24, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Pin-Hong Chen, Tsun-Min Cheng, Chih-Chieh Tsai, Tzu-Chieh Chen, Kai-Jiun Chang, Chia-Chen Wu, Yi-An Huang, Yi-Wei Chen
  • Patent number: 9859123
    Abstract: A method for fabricating a semiconductor device is disclosed. A substrate having a conductive region is provided. A metal layer is deposited on the conductive region. The metal layer reacts with the conductive region to form a first metal silicide layer. A TiN layer is deposited on the metal layer. A SiN layer is deposited on the TiN layer. An annealing process is performed to convert the first metal silicide layer into a second metal silicide layer.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: January 2, 2018
    Assignees: UNITED MICROELECTRONICS CORP., Fujian Jinhua Integrated Circuit Co., Ltd.
    Inventors: Chia-Chen Wu, Pin-Hong Chen, Kai-Jiun Chang, Yi-An Huang, Chih-Chieh Tsai, Tzu-Chieh Chen, Tsun-Min Cheng, Yi-Wei Chen