Patents by Inventor Chia Chen

Chia Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11930663
    Abstract: A display panel includes a first substrate, pixel structures, a first common pad, a second substrate, a second common electrode, a display medium and a conductive particle. The pixel structures are disposed on an active area of the first substrate. The first common pad is disposed on a peripheral area of the first substrate, and is electrically connected to first common electrodes of the pixel structures. The second common electrode is disposed on the second substrate. The conductive particle is disposed on the first common pad, and is electrically connected to the first common pad and the second common electrode. The conductive particle includes a core and a conductive film disposed on a surface of the core, where the conductive film has a main portion and raised portions, and a film thickness of each of the raised portions is greater than a film thickness of the main portion.
    Type: Grant
    Filed: April 9, 2021
    Date of Patent: March 12, 2024
    Assignee: Au Optronics Corporation
    Inventors: Bo-Chen Chen, Yun-Ru Cheng, Ya-Ling Hsu, Chia-Hsuan Pai, Cheng-Wei Huang, Wei-Shan Chao
  • Patent number: 11929216
    Abstract: A button mechanism includes a button, a module, and a thin sheet spring. The thin sheet spring is in physical communication with the button and with the module. The thin sheet spring exerts a tension force on the button and the module to bias the button toward a normal position. In response to a force greater than the tension force being exerted on the button, a portion of the thin sheet stretches to enable the button to be placed in a contact position. In response to the force being removed from the button, the tension force causes the thin sheet to snap back to an original position and biases the button toward the normal position.
    Type: Grant
    Filed: October 14, 2022
    Date of Patent: March 12, 2024
    Assignee: Dell Products L.P.
    Inventors: Minghao Hsieh, Chia-Chen Lin, Jer-Yo Lee, Po-Fei Tsai, Chang-Hsin Chen
  • Publication number: 20240079493
    Abstract: A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a gate structure disposed on the substrate. The semiconductor device also includes a source region and a drain region disposed within the substrate. The substrate includes a drift region laterally extending between the source region and the drain region. The semiconductor device further includes a first stressor layer disposed over the drift region of the substrate. The first stressor layer is configured to apply a first stress to the drift region of the substrate. In addition, the semiconductor device includes a second stressor layer disposed on the first stressor layer. The second stressor layer is configured to apply a second stress to the drift region of the substrate, and the first stress is opposite to the second stress.
    Type: Application
    Filed: September 1, 2022
    Publication date: March 7, 2024
    Inventors: GUAN-QI CHEN, CHEN CHI HSIAO, KUN-TSANG CHUANG, FANG YI LIAO, YU SHAN HUNG, CHUN-CHIA CHEN, YU-SHAN HUANG, TUNG-I LIN
  • Publication number: 20240079278
    Abstract: A method includes forming a pad layer. The pad layer includes a first portion over a first part of a semiconductor substrate, and a second portion over a second part of the semiconductor substrate. The first portion has a first thickness, and the second portion has a second thickness smaller than the first thickness. The semiconductor substrate is then annealed to form a first oxide layer over the first part of the semiconductor substrate, and a second oxide layer over the second part of the semiconductor substrate. The pad layer, the first oxide layer, and the second oxide layer are removed. A semiconductor layer is epitaxially grown over and contacting the first part and the second part of the semiconductor substrate.
    Type: Application
    Filed: January 6, 2023
    Publication date: March 7, 2024
    Inventors: Jhih-Yong Han, Wen-Yen Chen, Yi-Ting Wu, Tsai-Yu Huang, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11923886
    Abstract: An antenna device and a method for configuring the same are provided. The antenna device includes a grounding metal, a grounding part, a radiating part, a feeding part, a proximity sensor, and a sensing metal. The radiating part is electrically connected to the grounding metal through the grounding part. The feeding part is coupled to the grounding metal through a feeding point. The sensing metal is electrically connected to the proximity sensor. The sensing metal is separated from the radiating part at a distance. The distance is less than or equal to one thousandth of a wavelength corresponding to an operating frequency of the antenna device.
    Type: Grant
    Filed: August 27, 2021
    Date of Patent: March 5, 2024
    Assignee: COMPAL ELECTRONICS, INC.
    Inventors: Jhih-Ciang Chen, Shih-Chia Liu, Yen-Hao Yu, Li-Chun Lee, Yan-Ming Lin, Jui-Hung Lai
  • Patent number: 11923433
    Abstract: A method for manufacturing a semiconductor device includes forming a first dielectric layer over a semiconductor fin. The method includes forming a second dielectric layer over the first dielectric layer. The method includes exposing a portion of the first dielectric layer. The method includes oxidizing a surface of the second dielectric layer while limiting oxidation on the exposed portion of the first dielectric layer.
    Type: Grant
    Filed: March 9, 2021
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sheng-Liang Pan, Yungtzu Chen, Chung-Chieh Lee, Yung-Chang Hsu, Chia-Yang Hung, Po-Chuan Wang, Guan-Xuan Chen, Huan-Just Lin
  • Patent number: 11923199
    Abstract: Aspects of the disclosure provide a method. The method includes forming a structure over a substrate, and forming a spacer layer on the structure, wherein the spacer layer has a recess. The method includes forming a mask layer over the spacer layer and in the recess, the mask layer including a first layer, a second layer and a third layer. The method includes patterning the third layer of the mask layer, and etching the first layer and the second layer of the mask layer to form an opening to expose the recess of the spacer layer, wherein the opening in the second layer has a first width; and. The method includes removing the second layer using a wet etchant, wherein the opening in the third layer has a second width, and the second with is greater than the first width.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Nai-Chia Chen, Wan Hsuan Hsu, Chia-Wei Wu, Neng-Jye Yang, Chun-Li Chou
  • Publication number: 20240071408
    Abstract: A system may include a first acoustic event detection (AED) component configured to detect a predetermined set of acoustic events, and include a second AED component configured to detect custom acoustic events that a user configures a device to detect. The first and second AED components are configured to perform task-specific processing, and may receive as input the same acoustic feature data corresponding to audio data that potentially represents occurrence of one or more events. Based on processing by the first and second AED components, a device may output data indicating that one or more acoustic events occurred, where the acoustic events may be a predetermined acoustic event and/or a custom acoustic event.
    Type: Application
    Filed: September 8, 2023
    Publication date: February 29, 2024
    Inventors: Qingming Tang, Chieh-Chi Kao, Qin Zhang, Ming Sun, Chao Wang, Sumit Garg, Rong Chen, James Garnet Droppo, Chia-Jung Chang
  • Publication number: 20240072128
    Abstract: A method of forming a semiconductor device includes forming a source/drain region and a gate electrode adjacent the source/drain region, forming a hard mask over the gate electrode, forming a bottom mask over the source/drain region, wherein the gate electrode is exposed, and performing a nitridation process on the hard mask over the gate electrode. The bottom mask remains over the source/drain region during the nitridation process and is removed after the nitridation. The method further includes forming a silicide over the source/drain region after removing the bottom mask.
    Type: Application
    Filed: November 6, 2023
    Publication date: February 29, 2024
    Inventors: Tsan-Chun Wang, Su-Hao Liu, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11917422
    Abstract: An information handling system executing an intelligent throughput performance analysis and issue detection system may comprise a network interface device to establish a wireless link with a wireless network and a processor to execute a neural network trained to predict wireless link throughput values based on controlled connectivity testing metrics gathered in a controlled laboratory from tested information handling systems. The processor may gather measured throughput of the wireless link and operational connectivity metrics for the information handling system that describe antenna positional information, antenna adaptation controller parameters, signal strength measurements, and wireless link performance metrics. The neural network may output, based on the gathered operational connectivity metrics a predicted throughput value that differs from the measured throughput by a maximum tolerance.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: February 27, 2024
    Assignee: Dell Products, LP
    Inventors: Wei-Chia Huang, Chuang-Yueh Chen, YungShun Lin, Alan Eric Sicher, Lars Fredrik Proejts
  • Patent number: 11915942
    Abstract: A method of exposing a wafer to a high-tilt angle ion beam and an apparatus for performing the same are disclosed. In an embodiment, a method includes forming a patterned mask layer over a wafer, the patterned mask layer including a patterned mask feature; exposing the wafer to an ion beam, a surface of the wafer being tilted at a tilt angle with respect to the ion beam; and moving the wafer along a scan line with respect to the ion beam, a scan angle being defined between the scan line and an axis perpendicular to an axis of the ion beam, a difference between the tilt angle and the scan angle being less than 50°.
    Type: Grant
    Filed: June 30, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Cheng Chen, Wei-Ting Chien, Liang-Yin Chen, Huicheng Chang, Yee-Chia Yeo
  • Patent number: 11916031
    Abstract: A semiconductor device including a first die and a second die bonded to one another. The first die includes a first passivation layer over a substrate, and first bond pads in the first passivation layer. The second die includes a second passivation layer, which may be bonded to the first passivation layer, and second bond pads in the second passivation layer, which may be bonded to the first bond pads. The second bond pads include inner bond pads and outer bond pads. The outer bond pads may have a greater diameter than the inner bond pads as well as the first bond pads.
    Type: Grant
    Filed: May 16, 2022
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chia Hu, Ching-Pin Yuan, Sung-Feng Yeh, Sen-Bor Jan, Ming-Fa Chen
  • Patent number: 11913980
    Abstract: A power detection circuit is provided. The power detection circuit includes a comparator circuit operative to generate an output signal in response to an input signal. The output signal is configured to change from a first value to a second value in response to the input signal attaining a first threshold value. The output signal is configured to change from the second value to the first value in response to the input signal subsequently attaining a second threshold value. A current limiting circuit is connected to the comparator circuit and operative to limit a leakage current of the comparator circuit.
    Type: Grant
    Filed: March 6, 2023
    Date of Patent: February 27, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Chen Kuo, Chiting Cheng, Wei-jer Hsieh, Yangsyu Lin
  • Patent number: 11915064
    Abstract: The disclosure relates to processing application programming interface (API) requests. Embodiments include receiving, at an API wrapper, from a first caller, a first call to an API and sending the first call to the API. Embodiments include receiving, by the API wrapper, from one or more second callers, a second one or more calls to the API prior to receiving a response from the API to the first call. Embodiments include receiving, by the API wrapper, the response from the API to the first call and responding to the first call from the first caller with the response from the API to the first call. Embodiments include responding, by the API wrapper, to the second one or more calls from the one or more second callers with the response from the API to the first call without sending the second one or more calls to the API.
    Type: Grant
    Filed: February 17, 2022
    Date of Patent: February 27, 2024
    Assignee: VMware, Inc.
    Inventors: Yu Wu, Jin Feng, Sifan Liu, Zhiliang Zhang, Kai-chia Chen
  • Publication number: 20240065043
    Abstract: Embodiments described herein generally relate to sub-pixel circuits that may be utilized in a display such as an organic light-emitting diode (OLED) display. The device includes substrate, pixel-defining layer (PDL) structures disposed over the section of the substrate, inorganic or metal overhang structures disposed on an upper surface of the PDL structures, and a plurality of sub-pixels. The PDL structures include a trench disposed in the top surface of the PDL structure. Each sub-pixel includes an anode, an OLED material disposed over and in contact with the anode, and a cathode disposed over the OLED material. The inorganic or metal overhang structures have an overhang extension that extends laterally over the trench. An encapsulation layer is disposed over the cathode and extends under at least a portion of the inorganic or metal overhang structures and along a top surface of the PDL structures.
    Type: Application
    Filed: October 31, 2023
    Publication date: February 22, 2024
    Inventors: Ji-young CHOUNG, Jungmin LEE, Chung-chia CHEN, Yusin LIN, Dieter HAAS, Si Kyoung KIM
  • Publication number: 20240055230
    Abstract: Embodiments described herein relate to process systems for cleaning semiconductor process chamber components. The process systems include a process chamber having process chamber components. The process chamber components include a substrate support disposed within a chamber volume of the process chamber. A gas distribution assembly faces the substrate support. A gas baffle is fluidly coupled to the gas distribution assembly. A sensor system is coupled to the process chamber and is configured to monitor at least one characteristic of the volume of the process chamber. A dynamic gas assist is fluidly coupled to the gas baffle and is communicatively coupled to the sensor.
    Type: Application
    Filed: August 15, 2022
    Publication date: February 15, 2024
    Inventors: Jong Yun KIM, Kim Seong SIM, Roman M. MOSTOVOY, Won Ho SUNG, Pei-Chia CHEN
  • Publication number: 20240053190
    Abstract: A system includes a processor, and a display, a reader, a switch, a scale, a memory device, intake-type buttons and output-type buttons that are connected to the processor. The processor controls the display to display an identification number obtained by using the reader to read an identifier. The switch is operated to enable the processor to operate in an intake mode or an output mode. When operating in the intake (output) mode, the processor controls the display to display a symbol corresponding to one of the intake-type (output-type) buttons that is determined to be pressed, and in response to receipt of weight data from the scale, controls the display to display a value of pre-intake (post-output) weight obtained based on the weight data, and stores the value of pre-intake (post-output) weight in the memory device.
    Type: Application
    Filed: August 7, 2023
    Publication date: February 15, 2024
    Inventors: Ying-Li LEE, Jiun-Hung LIN, Chun-Hao LU, Yen-Jung LU, Chia-Chen HSU, Chih-Yi LI, Ching-Yu LEE, Chia-Chi CHANG, Ya-Wen KUNG, Li-Chien YANG, Huey-Jeng YANG
  • Patent number: 11901437
    Abstract: A semiconductor device includes a gate structure on a substrate, an offset spacer adjacent to the gate structure, a main spacer around the offset spacer, a source/drain region adjacent to two sides of the main spacer, a contact etch stop layer (CESL) adjacent to the main spacer, and an interlayer dielectric (ILD) layer around the CESL. Preferably, a dielectric constant of the offset spacer is higher than a dielectric constant of the main spacer.
    Type: Grant
    Filed: May 15, 2022
    Date of Patent: February 13, 2024
    Assignee: Marlin Semiconductor Limited
    Inventors: Te-Chang Hsu, Chun-Chia Chen, Yao-Jhan Wang
  • Patent number: 11901657
    Abstract: A connector includes a housing, a first electrode and a second electrode. The housing further includes a first body, bending parts, foolproof key positions, a second buckle, a first opening and a second opening. The first body forms a first accommodating space and a second accommodating space. The first accommodating space is provided with the foolproof key positions, the first opening, the second opening and the second buckle. The second buckle can be arranged corresponding to a first buckle of the wire end connector to buckle the wire end connector in the first accommodating space and the second accommodating space. The first electrode includes a first end and a third end, and the third end forms first current divider pins. The second electrode includes a second end and a fourth end, and the fourth end forms second current divider pins.
    Type: Grant
    Filed: March 31, 2022
    Date of Patent: February 13, 2024
    Assignee: P-TWO INDUSTRIES INC.
    Inventor: Chia-Chen Wei
  • Publication number: 20240047866
    Abstract: A combined streetlight, which is provided, is equipped with a cable set, a cable routing base, an equipment cabinet, and a frame. By combining and structurally designing of an attached equipment installation component, an antenna assembly, and other components, it can meet the installation requirements of various network devices and related equipment in smart cities. Additionally, by combining and structurally designing components of an installation structure shielding enclosure, it can achieve aesthetic appeal to meet urban aesthetics. Therefore, the proposed combined streetlight is suitable for use in the construction of smart cities.
    Type: Application
    Filed: August 2, 2023
    Publication date: February 8, 2024
    Inventors: HUNG-HSIANG CHIANG, CHIA-CHEN LIN, TSUNG-HSUN KUO, KAI-YUAN KUO