Patents by Inventor Chia-Cheng Chou

Chia-Cheng Chou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12255138
    Abstract: A method of forming an interconnect structure includes the following steps. A first etching stop layer, a first dielectric layer, a second etching stop layer, an insert layer and a second dielectric layer are deposited over the second etching stop layer are deposited over a substrate. The second dielectric layer, the insert layer, the second etching stop layer, the first dielectric layer and the first etching stop layer are patterned thereby forming a trench opening and a via hole. A conductive feature is filled in the trench opening and the via hole thereby forming a conductive line in the second dielectric layer and the insert layer and a via in the first etching stop layer and the first dielectric layer. A material of the insert layer is different from the second dielectric layer and the second etching stop layer.
    Type: Grant
    Filed: September 26, 2023
    Date of Patent: March 18, 2025
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chou, Chung-Chi Ko, Tze-Liang Lee
  • Publication number: 20240371769
    Abstract: A method for manufacturing an extra low-k (ELK) inter-metal dielectric (IMD) layer includes forming a first IMD layer including a plurality of dielectric material layers over a substrate. An adhesion layer is formed over the first IMD layer. An ELK dielectric layer is formed over the adhesion layer. A protection layer is formed over the ELK dielectric layer. A hard mask is formed over the protection layer and is patterned to create a window. Layers underneath the window are removed to create an opening. The removed layers include the protection layer, the ELK dielectric layer, the adhesion layer, and the first IMD layer. A metal layer is formed in the opening.
    Type: Application
    Filed: July 15, 2024
    Publication date: November 7, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Po-Cheng SHIH, Chia Cheng CHOU, Chun-Te LI
  • Patent number: 12062613
    Abstract: A method for manufacturing an extra low-k (ELK) inter-metal dielectric (IMD) layer includes forming a first IMD layer including a plurality of dielectric material layers over a substrate. An adhesion layer is formed over the first IMD layer. An ELK dielectric layer is formed over the adhesion layer. A protection layer is formed over the ELK dielectric layer. A hard mask is formed over the protection layer and is patterned to create a window. Layers underneath the window are removed to create an opening. The removed layers include the protection layer, the ELK dielectric layer, the adhesion layer, and the first IMD layer. A metal layer is formed in the opening.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: August 13, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Po-Cheng Shih, Chia Cheng Chou, Chun-Te Li
  • Publication number: 20240213161
    Abstract: A semiconductor device including a substrate, a low-k dielectric layer, a cap layer, and a conductive layer is provided. The low-k dielectric layer is disposed over the substrate. The cap layer is disposed on the low-k dielectric layer, wherein a carbon atom content of the cap layer is greater than a carbon atom content of the low-k dielectric layer. The conductive layer is disposed in the cap layer and the low-k dielectric layer.
    Type: Application
    Filed: February 5, 2024
    Publication date: June 27, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chou, Chung-Chi Ko, Tze-Liang Lee, Ming-Tsung Lee
  • Publication number: 20240178059
    Abstract: A structure includes a first conductive feature, a first etch stop layer over the first conductive feature, a dielectric layer over the first etch stop layer, and a second conductive feature in the dielectric layer and the first etch stop layer. The second conductive feature is over and contacting the first conductive feature. An air spacer encircles the second conductive feature, and sidewalls of the second conductive feature are exposed to the air spacer. A protection ring further encircles the second conductive feature, and the protection ring fully separates the second conductive feature from the air spacer.
    Type: Application
    Filed: February 2, 2024
    Publication date: May 30, 2024
    Inventors: Chia Cheng Chou, Chung-Chi Ko, Tze-Liang Lee
  • Patent number: 11929329
    Abstract: A semiconductor device including a substrate, a low-k dielectric layer, a cap layer, and a conductive layer is provided. The low-k dielectric layer is disposed over the substrate. The cap layer is disposed on the low-k dielectric layer, wherein a carbon atom content of the cap layer is greater than a carbon atom content of the low-k dielectric layer. The conductive layer is disposed in the cap layer and the low-k dielectric layer.
    Type: Grant
    Filed: May 28, 2020
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chou, Chung-Chi Ko, Tze-Liang Lee, Ming-Tsung Lee
  • Patent number: 11929281
    Abstract: A structure includes a first conductive feature, a first etch stop layer over the first conductive feature, a dielectric layer over the first etch stop layer, and a second conductive feature in the dielectric layer and the first etch stop layer. The second conductive feature is over and contacting the first conductive feature. An air spacer encircles the second conductive feature, and sidewalls of the second conductive feature are exposed to the air spacer. A protection ring further encircles the second conductive feature, and the protection ring fully separates the second conductive feature from the air spacer.
    Type: Grant
    Filed: September 21, 2021
    Date of Patent: March 12, 2024
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia Cheng Chou, Chung-Chi Ko, Tze-Liang Lee
  • Patent number: 11923294
    Abstract: An interconnect structure includes an etching stop layer, a dielectric layer and an insert layer and a conductive line. The insert layer is located between the etching stop layer and the dielectric layer. The conductive line extends through the dielectric layer, the insert layer, and the etching stop layer. A material of the insert layer is different from the dielectric layer and the etching stop layer.
    Type: Grant
    Filed: April 29, 2022
    Date of Patent: March 5, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chou, Chung-Chi Ko, Tze-Liang Lee
  • Publication number: 20240014125
    Abstract: A method of an interconnect structure includes the following steps. A first etching stop layer, a first dielectric layer, a second etching stop layer, an insert layer and a second dielectric layer are deposited over the second etching stop layer are deposited over a substrate. The second dielectric layer, the insert layer, the second etching stop layer, the first dielectric layer and the first etching stop layer are patterned thereby forming a trench opening and a via hole. A conductive feature is filled in the trench opening and the via hole thereby forming a conductive line in the second dielectric layer and the insert layer and a via in the first etching stop layer and the first dielectric layer. A material of the insert layer is different from the second dielectric layer and the second etching stop layer.
    Type: Application
    Filed: September 26, 2023
    Publication date: January 11, 2024
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chou, Chung-Chi Ko, Tze-Liang Lee
  • Publication number: 20230154765
    Abstract: A method includes bonding a first wafer to a second wafer, and performing a trimming process on the first wafer. An edge portion of the first wafer is removed. After the trimming process, the first wafer has a first sidewall laterally recessed from a second sidewall of the second wafer. A protection layer is deposited and contacting a sidewall of the first wafer, which deposition process includes depositing a non-oxygen-containing material in contact with the first sidewall. The method further includes removing a horizontal portion of the protection layer that overlaps the first wafer, and forming an interconnect structure over the first wafer. The interconnect structure is electrically connected to integrated circuit devices in the first wafer.
    Type: Application
    Filed: February 16, 2022
    Publication date: May 18, 2023
    Inventors: Chia Cheng Chou, Chung-Chi Ko, Tze-Liang Lee
  • Publication number: 20220406647
    Abstract: A structure includes a first conductive feature, a first etch stop layer over the first conductive feature, a dielectric layer over the first etch stop layer, and a second conductive feature in the dielectric layer and the first etch stop layer. The second conductive feature is over and contacting the first conductive feature. An air spacer encircles the second conductive feature, and sidewalls of the second conductive feature are exposed to the air spacer. A protection ring further encircles the second conductive feature, and the protection ring fully separates the second conductive feature from the air spacer.
    Type: Application
    Filed: September 21, 2021
    Publication date: December 22, 2022
    Inventors: Chia Cheng Chou, Chung-Chi Ko, Tze-Liang Lee
  • Publication number: 20220359412
    Abstract: A method for manufacturing an extra low-k (ELK) inter-metal dielectric (IMD) layer includes forming a first IMD layer including a plurality of dielectric material layers over a substrate. An adhesion layer is formed over the first IMD layer. An ELK dielectric layer is formed over the adhesion layer. A protection layer is formed over the ELK dielectric layer. A hard mask is formed over the protection layer and is patterned to create a window. Layers underneath the window are removed to create an opening. The removed layers include the protection layer, the ELK dielectric layer, the adhesion layer, and the first IMD layer. A metal layer is formed in the opening.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Inventors: Po-Cheng SHIH, Chia Cheng CHOU, Li Chun TE
  • Publication number: 20220316111
    Abstract: A woven brushed elastic fabric includes a fabric blank and a plurality of yarn segments. The fabric blank is formed by interweaving a plurality of first yarns and composite yarns. Each composite yarn is composed of a second yarn and an elastic yarn. The second yarn is wound around the elastic yarn. The fabric blank has a first side, and a second side opposite to the first side and formed with a plurality of yarn loops. The yarn loops are formed by the interweaving of the first yarns and the composite yarns in a skip manner along a first direction or a second direction transverse to the first direction. The yarn segments are formed on the second side of the fabric blank by breaking at least some of the yarn loops.
    Type: Application
    Filed: June 17, 2022
    Publication date: October 6, 2022
    Inventors: Kuo-Chin CHEN, Sung-Yun HUANG, Chia-Cheng CHOU, Chih-Wei CHEN, Li-Hsun CHANG
  • Publication number: 20220262725
    Abstract: An interconnect structure includes an interconnect structure includes an etching stop layer, a dielectric layer and an insert layer and a conductive line. The insert layer is located between the etching stop layer and the dielectric layer. The conductive line extends through the dielectric layer, the insert layer, and the etching stop layer. A material of the insert layer is different from the dielectric layer and the etching stop layer.
    Type: Application
    Filed: April 29, 2022
    Publication date: August 18, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chou, Chung-Chi Ko, Tze-Liang Lee
  • Patent number: 11417602
    Abstract: A method for manufacturing an extra low-k (ELK) inter-metal dielectric (IMD) layer includes forming a first IMD layer including a plurality of dielectric material layers over a substrate. An adhesion layer is formed over the first IMD layer. An ELK dielectric layer is formed over the adhesion layer. A protection layer is formed over the ELK dielectric layer. A hard mask is formed over the protection layer and is patterned to create a window. Layers underneath the window are removed to create an opening. The removed layers include the protection layer, the ELK dielectric layer, the adhesion layer, and the first IMD layer. A metal layer is formed in the opening.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: August 16, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Po-Cheng Shih, Chia Cheng Chou, Li Chun Te
  • Patent number: 11373947
    Abstract: An interconnect structure includes an interconnect structure includes an etching stop layer; a dielectric layer and an insert layer on the etching stop layer, and a conductive feature in the dielectric layer, the insert layer and the etching stop layer. A material of the insert layer is different from the dielectric layer and the etching stop layer.
    Type: Grant
    Filed: February 26, 2020
    Date of Patent: June 28, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chou, Chung-Chi Ko, Tze-Liang Lee
  • Patent number: 11328952
    Abstract: A device, structure, and method are provided whereby an insert layer is utilized to provide additional support for surrounding dielectric layers. The insert layer may be applied between two dielectric layers. Once formed, trenches and vias are formed within the composite layers, and the insert layer will help to provide support that will limit or eliminate undesired bending or other structural motions that could hamper subsequent process steps, such as filling the trenches and vias with conductive material.
    Type: Grant
    Filed: November 16, 2020
    Date of Patent: May 10, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chia-Cheng Chou, Chih-Chien Chi, Chung-Chi Ko, Yao-Jen Chang, Chen-Yuan Kao, Kai-Shiang Kuo, Po-Cheng Shih, Tze-Liang Lee, Jun-Yi Ruan
  • Publication number: 20210375779
    Abstract: A semiconductor device including a substrate, a low-k dielectric layer, a cap layer, and a conductive layer is provided. The low-k dielectric layer is disposed over the substrate. The cap layer is disposed on the low-k dielectric layer, wherein a carbon atom content of the cap layer is greater than a carbon atom content of the low-k dielectric layer. The conductive layer is disposed in the cap layer and the low-k dielectric layer.
    Type: Application
    Filed: May 28, 2020
    Publication date: December 2, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Cheng Chou, Chung-Chi Ko, Tze-Liang Lee, Ming-Tsung Lee
  • Publication number: 20210265264
    Abstract: An interconnect structure includes an interconnect structure includes an etching stop layer; a dielectric layer and an insert layer on the etching stop layer, and a conductive feature in the dielectric layer, the insert layer and the etching stop layer. A material of the insert layer is different from the dielectric layer and the etching stop layer.
    Type: Application
    Filed: February 26, 2020
    Publication date: August 26, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Cheng Chou, Chung-Chi Ko, Tze-Liang Lee
  • Patent number: 11062901
    Abstract: Embodiments described herein relate generally to methods for forming low-k dielectrics and the structures formed thereby. In some embodiments, a dielectric is formed over a semiconductor substrate. The dielectric has a k-value equal to or less than 3.9. Forming the dielectric includes using a plasma enhanced chemical vapor deposition (PECVD). The PECVD includes flowing a diethoxymethylsilane (mDEOS, C5H14O2Si) precursor gas, flowing an oxygen (O2) precursor gas; and flowing a carrier gas. A ratio of a flow rate of the mDEOS precursor gas to a flow rate of the carrier gas is less than or equal to 0.2.
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: July 13, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia Cheng Chou, Po-Cheng Shih, Li Chun Te, Tien-I Bao