Abstract: A semiconductor device is disclosed. The device includes a substrate, a first porous SiCOH dielectric layer, a second porous SiCOH dielectric layer, and an oxide layer. The first porous SiCOH dielectric layer overlies the substrate. The second porous SiCOH dielectric layer overlies the first porous SiCOH dielectric layer. The oxide layer overlies the second porous SiCOH dielectric layer. The atomic percentage of carbon in the second porous SiCOH dielectric layer is between 16% and 22% of that in the first porous SiCOH dielectric layer.

Abstract: A system and method for improving the performance of an integrated circuit by lowering RC delay time is provided. A preferred embodiment comprises adding a reactive etch gas to the ash/flush plasma process following a low-k dielectric etch. The illustrative embodiments implement a removal of the damage layer that is formed during a low-k dielectric etch.

Abstract: Interconnect structures are provided. An exemplary embodiment of an interconnect structure comprises a substrate with a low-k dielectric layer thereon. A via opening and a trench opening are formed in the low-k dielectric layer, wherein the trench opening is formed over the via opening and the via opening exposes a portion of the substrate. A liner layer is formed on sidewalls of the low-k dielectric layer exposed by the trench and via protions and a bottom surface exposed by the trench via portion, wherein the portion of the liner layer on sidewalls of the low-k dielectric layer exposed by the trench and via protions and the portion of the liner layer formed on a bottom surface exposed by the trench portion comprise different materials. A conformal conductive barrier layer is formed in the trench and via openings, covering the liner layer and the exposed portion of the substrate. A conductive layer is formed on the conductive barrier layer, filling in the trench and via openings.

Abstract: A semiconductor device is disclosed. The device includes a substrate, a first porous SiCOH dielectric layer, a second porous SiCOH dielectric layer, and an oxide layer. The first porous SiCOH dielectric layer overlies the substrate. The second porous SiCOH dielectric layer overlies the first porous SiCOH dielectric layer. The oxide layer overlies the second porous SiCOH dielectric layer. The atomic percentage of carbon in the second porous SiCOH dielectric layer is between 16% and 22% of that in the first porous SiCOH dielectric layer.

Abstract: A bilayer porous low dielectric constant (low-k) interconnect structure and methods of fabricating the same are presented. A preferred embodiment having an effective dielectric constant of about 2.2 comprises a bottom deposited dielectric layer and a top deposited dielectric layer in direct contact with the former. The bottom layer and the top layer have same atomic compositions, but a higher dielectric constant value k. The bottom dielectric layer serves as an etch stop layer for the top dielectric layer, and the top dielectric layer can act as CMP stop layer. One embodiment of making the structure includes forming a bottom dielectric layer having a first porogen content and a top dielectric layer having a higher porogen content. A curing process leaves lower pore density in the bottom dielectric layer than that left in the top dielectric layer, which leads to higher dielectric value k in the bottom dielectric layer.

Abstract: A method for forming an integrated circuit includes forming a low-k dielectric layer over a semiconductor substrate, etching the low-k dielectric layer to form an opening, forming a dielectric barrier layer covering at least sidewalls of the opening, performing a treatment to improve a wetting ability of the dielectric barrier layer, and filling the opening with a conductive material, wherein the conductive material is in contact with the dielectric barrier layer.

Abstract: Interconnect structures are provided. An exemplary embodiment of an interconnect structure comprises a substrate with a low-k dielectric layer thereon. A via opening and a trench opening are formed in the low-k dielectric layer, wherein the trench opening is formed over the via opening and-the via opening exposes a portion of the substrate. A liner layer is formed on sidewalls of the low-k dielectric layer exposed by the trench and via protions and a bottom surface exposed by the trench via portion, wherein the portion of the liner layer on sidewalls of the low-k dielectric layer exposed by the trench and via protions and the portion of the liner layer formed on a bottom surface exposed by the trench portion comprise different materials. A conformal conductive barrier layer is formed in the trench and via openings, covering the liner layer and the exposed portion of the substrate.

Abstract: A method of forming a low-k dielectric layer and forming a structure in the low-k dielectric layer includes depositing a low-k dielectric layer over a substrate, performing a first treatment to the low-k dielectric layer, performing post-formation processes, and performing a second treatment to the low-k dielectric layer. The k value of the low-k dielectric layer is lowered by the first treatment. The post-formation processes performed to the low-k dielectric layer include at least one low-k dielectric material damaging process. The second treatment restores the low-k dielectric layer. Preferably, each of the first and second treatments includes a curing process selected from e-beam curing, ultraviolet curing, plasma curing, SCCO2 cleaning, and combinations thereof.

Abstract: An interconnect structure of an integrated circuit includes a low-k dielectric layer over a semiconductor substrate, a conductor in the low-k dielectric layer, and a dielectric transition layer between the low-k dielectric layer and the conductor, wherein the dielectric transition layer has a thickness of less than about 50 ?.

Abstract: A method of forming a low-k dielectric layer or film includes forming a porous low-k dielectric layer or film over a wafer or substrate. Active bonding is introduced into the porous low-k dielectric layer or fihm to improve damage resistance and chemical integrity of the layer or film, to retain the low dielectric constant of the layer and film after subsequent processing. Introduction of the active bonding may be accomplished by introducing OH and/or H radicals into pores of the porous low-k dielectric layer or film to generate, in the case of a Si based low-k dielectric layer or film, Si—OH and/or Si—H active bonds. After further processing of the low-k dielectric film, the active bonding is removed from the low-k dielectric layer or film.

Abstract: A method of forming a low-k dielectric layer and forming a structure in the low-k dielectric layer includes depositing a low-k dielectric layer over a substrate, performing a first treatment to the low-k dielectric layer, performing post-formation processes, and performing a second treatment to the low-k dielectric layer. The k value of the low-k dielectric layer is lowered by the first treatment. The post-formation processes performed to the low-k dielectric layer include at least one low-k dielectric material damaging process. The second treatment restores the low-k dielectric layer. Preferably, each of the first and second treatments includes a curing process selected from e-beam curing, ultraviolet curing, plasma curing, SCCO2 cleaning, and combinations thereof.