Abstract: A method is disclosed for etching an integrated circuit structure within a trench. A layer to be etched is applied over the structure and within the trench. A CF-based polymer is deposited over the layer to be etched followed by deposition of a capping layer of SiOCl-based polymer. The CF-based polymer reduces the width of the trench to such an extent that little or no SiOCl-based polymer is deposited at the bottom of the trench. An O2 plasma etch is performed to etch through the CF-based polymer at the bottom of the trench. The O2 plasma etch has little effect on the SiOCl-based polymer, the thus the upper surfaces of the structure remain covered with polymer. Thus, these upper surfaces remain fully protected during subsequent etching of the layer to be etched.

Abstract: A method of fabricating a semiconductor device is illustrated. A substrate having a plurality of trenches is provided. The plurality of trenches include trenches having differing widths. A first layer is formed on the substrate including in the plurality of trenches. Forming the first layer creates an indentation in the first layer in a region overlying a trench (e.g., wide trench). A second layer is formed in the indentation. The first layer is etched while the second layer remains in the indentation. The second layer may protect the region of indentation from further reduction in thickness. In an embodiment, the first layer is polysilicon and the second layer is BARC of photoresist.

Abstract: A light amount adjusting component adapted a projection optical system is provided. The light amount adjusting component has a light incident surface upon which a light beam impinges, and the light incident surface is provided with a surface structure for irregularly dispersing the light beam. A slot that permits the light beam to pass therethrough and enter a light-receiving element is formed on the light amount adjusting component, and a width of the slot changes along an extension direction of the slot to allow control of the amount of the light beam entering the light-receiving element when the light amount adjusting component moves or rotates.

Abstract: A light amount adjusting component adapted a projection optical system is provided. The light amount adjusting component has a light incident surface upon which a light beam impinges, and the light incident surface is provided with a surface structure for irregularly dispersing the light beam. A slot that permits the light beam to pass therethrough and enter a light-receiving element is formed on the light amount adjusting component, and a width of the slot changes along an extension direction of the slot to allow control of the amount of the light beam entering the light-receiving element when the light amount adjusting component moves or rotates.

Abstract: A method is disclosed for etching an integrated circuit structure within a trench. A layer to be etched is applied over the structure and within the trench. A CF-based polymer is deposited over the layer to be etched followed by deposition of a capping layer of SiOCl-based polymer. The CF-based polymer reduces the width of the trench to such an extent that little or no SiOCl-based polymer is deposited at the bottom of the trench. An O2 plasma etch is performed to etch through the CF-based polymer at the bottom of the trench. The O2 plasma etch has little effect on the SiOCl-based polymer, the thus the upper surfaces of the structure remain covered with polymer. Thus, these upper surfaces remain fully protected during subsequent etching of the layer to be etched.

Abstract: Provided is a method of fabricating a memory device. A substrate including an array region and a peripheral region is provided. A first feature and a second feature are formed in the array region. The first feature and the second feature have a first pitch. A plurality of spacers abutting each of the first feature and the second feature are formed. The plurality of spacers have a second pitch. A third feature in the peripheral region and a fourth and fifth feature in the array region are formed concurrently. The forth and fifth feature have the second pitch.

Abstract: Provided is a semiconductor interconnect structure formed from an original damascene or dual damascene structure. The original damascene or dual damascene structure includes a planar upper surface consisting of planar upper surfaces of conductive structures formed within openings formed in the dielectric, and planar upper surfaces of the dielectric. The original structure is processed using wet or dry etching operations which, by including ion bombardment and/or ion milling characteristics, both etch the upper dielectric surface and round the upper edges of the originally formed interconnect structures that become exposed as the dielectric is etched. Produced is an interconnect structure within an opening formed in a dielectric and which includes an upper portion that extends above the dielectric and includes opposed upper edges that are rounded.

Abstract: A dual damascene process for fabricating a semiconductor device. A dielectric layer is formed on a substrate, comprising at least one via opening therein. A trench opening is formed in the dielectric layer above the via opening and the via opening widened by in-situ etching.

Abstract: Methods for making a nonvolatile memory device, such as an NROM device that has an oxide-nitride-oxide layer beneath at least one word line structure, are disclosed. The oxide-nitride-oxide layer is in the form of a plurality of oxide-nitride block structures disposed over an oxide layer, with each of the oxide-nitride block structures overlapping two adjoining bit lines. A dielectric resolution enhancement coating technique is performed to precisely control the oxide-nitride block structure dimensions.

Abstract: Methods for making a nonvolatile memory device, such as an NROM device that has an oxide-nitride-oxide layer beneath at least one word line structure, are disclosed. The oxide-nitride-oxide layer is in the form of a plurality of oxide-nitride block structures disposed over an oxide layer, with each of the oxide-nitride block structures overlapping two adjoining bit lines. A dielectric resolution enhancement coating technique is performed to precisely control the oxide-nitride block structure dimensions.

Abstract: The present invention generally relates to a dual damascene processing method using a silicon rich oxide (SRO) layer thereof and its structure. In the dual damascene process, a first dielectric layer, an etching stop layer, such as a silicon rich oxide layer, and a second dielectric layer are sequentially formed on a semiconductor substrate, which is provided with metal connections therein. Then, the present invention utilizes photolithography and etching technique to obtain a dual damascene structure profile having a trench and a via hole. The present invention uses the silicon rich oxide layer as the etching stop layer so as the present invention can achieve a better trench microloading and better bottom profile. Beside, the present invention does not increase the dielectric constant index (K) of the inter metal dielectric (IMD).

Abstract: A method for forming a self-aligned contact (SAC)/borderless contact opening includes forming a shallow trench isolation (STI) structure in a substrate to define an active area. A gate structure including a cap layer is formed. The gate structure is formed on the substrate and oriented perpendicular to the STI structure and the active area. An oxide spacer is formed on at least one of the sidewalls of the gate structure. A conformal liner layer is formed on the substrate covering the gate structure, the oxide spacer, and the STI structure. An inter-layer dielectric (ILD) layer is formed on the substrate covering the liner layer. The ILD layer is patterned and etched to define a SAC/borderless contact opening. A SAC/borderless contact opening structure also is described.

Abstract: A method is disclosed for forming a semiconductor structure with conductive features having reduced dimensional spacing or pitch. First polymer layers are formed over photoresist features to facilitate patterning of both an underlying first dielectric and conductive layer into first dielectric features and conductive features. Second dielectric features are then formed in spaces between the first dielectric and between the conductive features, followed by the first dielectric features being removed. Second polymer layers are then formed over the second dielectric features, such that portions of the second polymer layers cover corresponding portions of the conductive features that are adjacent to the second dielectric features. Subsequently, the second polymer layers are used to pattern the conductive features, to thereby remove portions of the conductive features that are not covered by the polymer layers and define second conductive features.

Abstract: Methods for making a nonvolatile memory device, such as an NROM device that has an oxide-nitride-oxide layer beneath at least one word line structure, are disclosed. The oxide-nitride-oxide layer is in the form of a plurality of oxide-nitride block structures disposed over an oxide layer, with each of the oxide-nitride block structures overlapping two adjoining bit lines. A dielectric resolution enhancement coating technique is performed to precisely control the oxide-nitride block structure dimensions.

Abstract: A method for pulling back SiN to increase rounding effect in a shallow trench isolation process, includes the steps of preparing a substrate of Si and forming a SiO2 layer on the substrate, forming a Si3N4 layer on the SiO2 layer, defining Si3N4 trenches by plasma etching, etching the remaining Si3N4 with SF6/HBr gas, etching SiO2 layer to form a platform and enhance the rounding of the platform, etching the substrate to have a third shallow trench and a reinforced platform, filling the third shallow trench with oxide, planarizing the filled oxide using chemical mechanical polishing, and removing the Si3N4 layer, wherein after the removal of the Si3N4 layer, multiple cleaning processes are performed.

Abstract: A method is disclosed for forming a semiconductor structure with conductive features having reduced dimensional spacing or pitch. First polymer layers are formed over photoresist features to facilitate patterning of both an underlying first dielectric and conductive layer into first dielectric features and conductive features. Second dielectric features are then formed in spaces between the first dielectric and between the conductive features, followed by the first dielectric features being removed. Second polymer layers are then formed over the second dielectric features, such that portions of the second polymer layers cover corresponding portions of the conductive features that are adjacent to the second dielectric features. Subsequently, the second polymer layers are used to pattern the conductive features, to thereby remove portions of the conductive features that are not covered by the polymer layers and define second conductive features.

Abstract: A method for pull back SiN to increase rounding effect in a shallow trench isolation process, includes the acts of preparing a substrate of Si and forming a SiO2 layer on the substrate, forming a Si3N4 layer on the SiO2 layer, defining Si3N4 trenches by plasma etching; etching the remaining Si3N4 with SF6/HBr gas, etching SiO2 layer to form a platform and enhance the rounding of the platform, etching the substrate to have a third shallow trench and a reinforced platform, filling the third shallow trench with oxide, leveling the oxide, which uses a CMP to level the filled oxide, and removing the Si3N4 layer, wherein after the removal of the Si3N4 layer, multiple cleaning processes are required.

Abstract: The present invention generally relates to a dual damascene processing method using a silicon rich oxide (SRO) layer thereof and its structure. In the dual damascene process, a first dielectric layer, an etching stop layer, such as a silicon rich oxide layer, and a second dielectric layer are sequentially formed on a semiconductor substrate, which is provided with metal connections therein. Then, the present invention utilizes photolithography and etching technique to obtain a dual damascene structure profile having a trench and a via hole. The present invention uses the silicon rich oxide layer as the etching stop layer so as the present invention can achieve a better trench microloading and better bottom profile. Beside, the present invention does not increase the dielectric constant index (K) of the inter metal dielectric (IMD).

Abstract: Methods for making a nonvolatile memory device, such as an NROM device that has an oxide-nitride-oxide layer beneath at least one word line structure, are disclosed. The oxide-nitride-oxide layer is in the form of a plurality of oxide-nitride block structures disposed over an oxide layer, with each of the oxide-nitride block structures overlapping two adjoining bit lines. A dielectric resolution enhancement coating technique is performed to precisely control the oxide-nitride block structure dimensions.

Abstract: A semiconductor manufacturing process that includes providing an insulating material, providing a first photoresist over the insulating material, defining and patterning the first photoresist, anisotropically etching the insulating material to form at least one groove in the insulating material, removing the first photoresist, providing a second photoresist over the insulating material, defining and patterning the second photoresist to form a plurality of tops and sidewalls, depositing a layer of carbon-fluoride material over the tops and sidewalls of the defined and patterned second photoresist, and anisotropically etching the insulating layer to form at least one opening, wherein the at least one opening is aligned with the at least one groove.