Patents by Inventor Chia-Chi Huang

Chia-Chi Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11152417
    Abstract: The present disclosure is directed to anchor structures and methods for forming anchor structures such that planarization and wafer bonding can be uniform. Anchor structures can include anchor layers formed on a dielectric layer surface and anchor pads formed in the anchor layer and on the dielectric layer surface. The anchor layer material can be selected such that the planarization selectivity of the anchor layer, anchor pads, and the interconnection material can be substantially the same as one another. Anchor pads can provide uniform density of structures that have the same or similar material.
    Type: Grant
    Filed: August 6, 2018
    Date of Patent: October 19, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yu Wei, Cheng-Yuan Li, Hsin-Chi Chen, Kuo-Cheng Lee, Hsun-Ying Huang, Yen-Liang Lin
  • Patent number: 11151724
    Abstract: An automatic detecting method and an automatic detecting apparatus using the same are provided. The automatic detecting apparatus includes an inputting unit, a dividing unit, a contouring unit, a range analyzing unit, a boundary analyzing unit, an edge detecting unit, an expanding unit and an overlapping unit. The dividing unit is used for dividing an overlooking image into four clusters via a clustering algorithm. The contouring unit is used for obtaining a contour. The range analyzing unit is used for obtaining a detecting range. The boundary analyzing unit is used for obtaining a circular boundary in the detecting range. The edge detecting unit is used for obtaining a plurality of edges in the circular boundary. The expanding unit is used for expanding the edges to obtain a plurality of expanded edges. The overlapping unit is used for overlapping the expanded edges and the contour to obtain a defect pattern.
    Type: Grant
    Filed: June 3, 2019
    Date of Patent: October 19, 2021
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Tzu-Ping Kao, Ching-Hsing Hsieh, Chia-Chi Chang, Ju-Te Chen, Chen-Hui Huang, Cheng-Hsien Chen
  • Patent number: 11152475
    Abstract: A method includes providing a structure having a substrate, a gate, a gate spacer, a dielectric gate cap, a source/drain (S/D) feature, a contact etch stop layer (CESL) covering a sidewall of the gate spacer and a top surface of the S/D feature, and an inter-level dielectric (ILD) layer. The method includes etching a contact hole through the ILD layer and through a portion of the CESL, the contact hole exposing the CESL covering the sidewalls of the gate spacer and exposing a top portion of the S/D feature. The method includes forming a silicide feature on the S/D feature and selectively depositing an inhibitor on the silicide feature. The inhibitor is not deposited on surfaces of the CESL other than at a corner area where the CESL and the silicide feature meet.
    Type: Grant
    Filed: May 22, 2020
    Date of Patent: October 19, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 11145728
    Abstract: A method includes forming a gate structure over a fin protruding above a substrate, forming a gate spacer layer on sidewalls of the gate structure, forming an etch stop layer on sidewalls of the gate spacer layer, replacing the gate structure with a gate stack, forming a source/drain contact adjacent the etch stop layer, recessing the gate stack to form a first recess, filling the first recess with a first dielectric material, recessing the source/drain contact and the etch stop layer to form a second recess, filling the second recess with a second dielectric material, recessing the second dielectric material and the gate spacer layer to form a third recess, and filling the third recess with a third dielectric material, wherein the composition of the third dielectric material is different from that of the first dielectric material and the second dielectric material.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Publication number: 20210300622
    Abstract: The disclosure describes embodiments of an apparatus including a first gas chromatograph including a fluid inlet, a fluid outlet, and a first temperature control. A controller is coupled to the first temperature control and includes logic to apply a first temperature profile to the first temperature control to heat, cool, or both heat and cool the first gas chromatograph. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: June 9, 2021
    Publication date: September 30, 2021
    Inventors: Tsung-Kuan A. Chou, Shih-Chi Chu, Chia-Sheng Cheng, Li-Peng Wang, Chien-Lin Huang
  • Publication number: 20210305382
    Abstract: A semiconductor device includes a metal gate structure having sidewall spacers disposed on sidewalls of the metal gate structure. In some embodiments, a top surface of the metal gate structure is recessed with respect to a top surface of the sidewall spacers. The semiconductor device may further include a metal cap layer disposed over and in contact with the metal gate structure, where a first width of a bottom portion of the metal cap layer is greater than a second width of a top portion of the metal cap layer. In some embodiments, the semiconductor device may further include a dielectric material disposed on either side of the metal cap layer, where the sidewall spacers and a portion of the metal gate structure are disposed beneath the dielectric material.
    Type: Application
    Filed: September 30, 2020
    Publication date: September 30, 2021
    Inventors: Lin-Yu HUANG, Li-Zhen YU, Chia-Hao CHANG, Cheng-Chi CHUANG, Kuan-Lun CHENG, Chih-Hao WANG
  • Publication number: 20210273062
    Abstract: A method includes providing a structure having a substrate, a gate, a gate spacer, a dielectric gate cap, a source/drain (S/D) feature, a contact etch stop layer (CESL) covering a sidewall of the gate spacer and a top surface of the S/D feature, and an inter-level dielectric (ILD) layer. The method includes etching a contact hole through the ILD layer and through a portion of the CESL, the contact hole exposing the CESL covering the sidewalls of the gate spacer and exposing a top portion of the S/D feature. The method includes forming a silicide feature on the S/D feature and selectively depositing an inhibitor on the silicide feature. The inhibitor is not deposited on surfaces of the CESL other than at a corner area where the CESL and the silicide feature meet.
    Type: Application
    Filed: May 22, 2020
    Publication date: September 2, 2021
    Inventors: Lin-Yu Huang, Li-Zhen Yu, Chia-Hao Chang, Cheng-Chi Chuang, Yu-Ming Lin, Chih-Hao Wang
  • Patent number: 9653530
    Abstract: An OLED module equipped with vertical electric connection structure includes a substrate, a plurality of OLED clusters, an anode wire structure and a cathode wire structure. The substrate is extended toward a first direction. The OLED clusters are located on the substrate in the first direction. The anode wire structure includes a bottom layer wire set, an insulation layer, a middle wire layer set and a top layer wire set. The bottom layer wire set is located on the substrate. The insulation layer is located on the bottom layer wire set. The top layer wire set is located on the insulation layer. The cathode wire structure is located on the substrate and extended axially thereof. The middle layer wire set runs through the insulation layer and forms vertical connection between the bottom layer wire set and the top layer wire set.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: May 16, 2017
    Assignee: WiseChip Semiconductor Inc.
    Inventors: Po-Hsin Lin, Shih-Hung Chang, Shang-Chih Lin, Chia-Chi Huang, I-Hsuan Lin, Sheng-Hsu Shih, Chien-Hsun Chen, Yung-Cheng Tsai, Chien-Le Li
  • Patent number: 9508859
    Abstract: A TFT array substrate and a manufacturing method of the same are disclosed by the present disclosure. The TFT array substrate includes a base, a light shielding layer, and a low hydrogen layer. The light shielding layer includes a silicon nitride layer formed on the base, and an amorphous silicon light shielding layer formed on the silicon nitride layer. The low hydrogen layer includes a silicon oxide layer formed on the amorphous silicon light shielding layer of the light shielding layer, and a low hydrogen Poly-Si layer formed on the silicon oxide layer. The layer number of the light shielding layer is equal to that of the low hydrogen layer. The time of manufacturing the light shielding layer matched that of manufacturing the low hydrogen layer, which enhances whole capacity of the TFT array substrate dramatically, and reduces risk of the manufacturing process.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: November 29, 2016
    Assignee: EverDisplay Optronics (Shanghai) Limited
    Inventors: Chia-chi Huang, Min-ching Hsu
  • Publication number: 20160260793
    Abstract: An OLED module equipped with vertical electric connection structure includes a substrate, a plurality of OLED clusters, an anode wire structure and a cathode wire structure. The substrate is extended toward a first direction. The OLED clusters are located on the substrate in the first direction. The anode wire structure includes a bottom layer wire set, an insulation layer, a middle wire layer set and a top layer wire set. The bottom layer wire set is located on the substrate. The insulation layer is located on the bottom layer wire set. The top layer wire set is located on the insulation layer. The cathode wire structure is located on the substrate and extended axially thereof The middle layer wire set runs through the insulation layer and forms vertical connection between the bottom layer wire set and the top layer wire set.
    Type: Application
    Filed: February 3, 2016
    Publication date: September 8, 2016
    Inventors: Po-Hsin LIN, Shih-Hung CHANG, Shang-Chih LIN, Chia-Chi HUANG, I-Hsuan LIN, Sheng-Hsu SHIH, Chien-Hsun CHEN, Yung-Cheng TSAI, Chien-Le LI
  • Patent number: 9401376
    Abstract: The present application provides a thin film transistor, an active matrix organic light emitting diode assembly and a method for manufacturing the same. The thin film transistor includes: a substrate; a buffer layer on the substrate; a semiconductor layer on the buffer layer, including a source region, a drain region and a channel region; a first gate insulating layer covering the semiconductor layer; a second gate insulating layer foot on the first gate insulating layer, a width of the second gate insulating layer foot being smaller than a width of the first gate insulating layer; and a gate electrode on the second gate insulating layer foot; wherein a part of the first gate insulating layer that is on the semiconductor layer has a flat upper surface. The present application may obtain better implantation profiles of source region and drain region, thereby obtaining better uniformity in TFT performance.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: July 26, 2016
    Assignee: EverDisplay Optronics (Shanghai) Limited
    Inventors: Chia-Che Hsu, Chia-Chi Huang, Wei-Ting Chen, Min-Ching Hsu
  • Patent number: 9368602
    Abstract: Methods for fabricating an IGZO layer and fabricating TFT are provided in the present invention. The method for fabricating TFT includes the following steps: (1) depositing an IGZO layer and forming a surface oxidizing gas protective layer on the IGZO layer; (2) coating the IGZO layer with a photoresist, and then subjecting the photoresist to an exposing and developing process to form a photoresist pattern; and (3) subjecting the IGZO layer to an etching process, and then removing the photoresist. By forming an oxidizing gas protective layer, the present methods for fabricating an IGZO layer and fabricating TFT can effectively reduce the effect of hydrogen atom on IGZO layer and avoid the change of IGZO layer from semiconductor to conductor, thereby improving the stability of the IGZO layer and thus the TFT, and reducing the negative bias of threshold voltage generated by the long-term continuous use of the device.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: June 14, 2016
    Assignee: EverDisplay Optronics (Shanghai) Limited
    Inventors: Chia-chi Huang, Min-ching Hsu, Hsueh-ming Tsai, Wen-xia Zuo
  • Publication number: 20160118239
    Abstract: The present disclosure provides A gate insulating layer comprising: a first silicon nitride film having a first thickness and a first content of N—H bonds; a second silicon nitride film having a second thickness and a second content of N—H bonds, disposed on the first silicon nitride film; and a third silicon nitride film having a third thickness and a third content of N—H bonds, disposed on the second silicon nitride film; wherein both the first thickness and the third thickness are less than the second thickness, both the N—H bonds in the first content and the third content are less than that in the second N—H bonds content, and a difference of the N—H bonds between the third content and the first content is no less than 5%. The present disclosure also provides a method for forming the above gate insulating layer.
    Type: Application
    Filed: January 6, 2016
    Publication date: April 28, 2016
    Inventors: Wei-ting CHEN, Chia-chi HUANG, Chunchieh HUANG, Youyuan HU
  • Publication number: 20150311350
    Abstract: A TFT array substrate and a manufacturing method of the same are disclosed by the present disclosure. The TFT array substrate includes a base, a light shielding layer, and a low hydrogen layer. The light shielding layer includes a silicon nitride layer formed on the base, and an amorphous silicon light shielding layer formed on the silicon nitride layer. The low hydrogen layer includes a silicon oxide layer formed on the amorphous silicon light shielding layer of the light shielding layer, and a low hydrogen Poly-Si layer formed on the silicon oxide layer. The layer number of the light shielding layer is equal to that of the low hydrogen layer. The time of manufacturing the light shielding layer matched that of manufacturing the low hydrogen layer, which enhances whole capacity of the TFT array substrate dramatically, and reduces risk of the manufacturing process.
    Type: Application
    Filed: January 30, 2015
    Publication date: October 29, 2015
    Inventors: Chia-chi HUANG, Min-ching HSU
  • Patent number: 9159773
    Abstract: A thin film transistor includes a semiconductor layer including a source region, a drain region, a channel region, first lightly doped drain regions adjacent to the channel region and second lightly doped drain regions adjacent to the first lightly doped drain regions; wherein the second lightly doped drain regions have a doping concentration lower than that of the first lightly doped drain regions. According to the present application, the leakage current in a switching transistor may be further reduced, thereby avoiding instability and even failure in the operation of the assembly caused by overlarge leakage current.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: October 13, 2015
    Assignee: EverDisplay Optronics (Shanghai) Limited
    Inventors: Chia-che Hsu, Chia-chi Huang, Wei-ting Chen, Min-ching Hsu
  • Publication number: 20150129989
    Abstract: The present disclosure provides A gate insulating layer comprising: a first silicon nitride film having a first thickness and a first content of N—H bonds; a second silicon nitride film having a second thickness and a second content of N—H bonds, disposed on the first silicon nitride film; and a third silicon nitride film having a third thickness and a third content of N—H bonds, disposed on the second silicon nitride film; wherein both the first thickness and the third thickness are less than the second thickness, both the N—H bonds in the first content and the third content are less than that in the second N—H bonds content, and a difference of the N—H bonds between the third content and the first content is no less than 5%. The present disclosure also provides a method for forming the above gate insulating layer.
    Type: Application
    Filed: August 19, 2014
    Publication date: May 14, 2015
    Inventors: Wei-ting CHEN, Chia-chi HUANG, Chunchieh HUANG, Youyuan HU
  • Patent number: 8962990
    Abstract: The disclosure provides a multilayer composition containing fluoropolymer and method for fabricating the same, and a solar cell module. The multilayer composition includes: a fluoropolymer layer; a non-fluorinated polymer layer; and an adhesion promoter layer formed between the fluoropolymer layer and the non-fluorinated polymer layer, wherein the adhesion promoter layer includes aromatic diamines or aromatic polyamines.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: February 24, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Tien-Shou Shieh, Chia-Chi Huang
  • Publication number: 20150011047
    Abstract: Methods for fabricating an IGZO layer and fabricating TFT are provided in the present invention. The method for fabricating TFT includes the following steps: (1) depositing an IGZO layer and forming a surface oxidizing gas protective layer on the IGZO layer; (2) coating the IGZO layer with a photoresist, and then subjecting the photoresist to an exposing and developing process to form a photoresist pattern; and (3) subjecting the IGZO layer to an etching process, and then removing the photoresist. By forming an oxidizing gas protective layer, the present methods for fabricating an IGZO layer and fabricating TFT can effectively reduce the effect of hydrogen atom on IGZO layer and avoid the change of IGZO layer from semiconductor to conductor, thereby improving the stability of the IGZO layer and thus the TFT, and reducing the negative bias of threshold voltage generated by the long-term continuous use of the device.
    Type: Application
    Filed: June 27, 2014
    Publication date: January 8, 2015
    Inventors: Chia-chi HUANG, Min-ching HSU, Hsueh-ming TSAI, Wen-xia ZUO
  • Publication number: 20140374714
    Abstract: A thin film transistor includes a semiconductor layer including a source region, a drain region, a channel region, first lightly doped drain regions adjacent to the channel region and second lightly doped drain regions adjacent to the first lightly doped drain regions; wherein the second lightly doped drain regions have a doping concentration lower than that of the first lightly doped drain regions. According to the present application, the leakage current in a switching transistor may be further reduced, thereby avoiding instability and even failure in the operation of the assembly caused by overlarge leakage current.
    Type: Application
    Filed: June 6, 2014
    Publication date: December 25, 2014
    Inventors: Chia-che HSU, Chia-chi HUANG, Wei-ting CHEN, Min-ching HSU
  • Publication number: 20140374718
    Abstract: The present application provides a thin film transistor, an active matrix organic light emitting diode assembly and a method for manufacturing the same. The thin film transistor includes: a substrate; a buffer layer on the substrate; a semiconductor layer on the buffer layer, including a source region, a drain region and a channel region; a first gate insulating layer covering the semiconductor layer; a second gate insulating layer foot on the first gate insulating layer, a width of the second gate insulating layer foot being smaller than a width of the first gate insulating layer; and a gate electrode on the second gate insulating layer foot; wherein a part of the first gate insulating layer that is on the semiconductor layer has a flat upper surface. The present application may obtain better implantation profiles of source region and drain region, thereby obtaining better uniformity in TFT performance.
    Type: Application
    Filed: June 19, 2014
    Publication date: December 25, 2014
    Inventors: Chia-Che HSU, Chia-Chi HUANG, Wei-Ting CHEN, Min-Ching HSU