Patents by Inventor Chia-Chi Huang

Chia-Chi Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190157103
    Abstract: A planarization method and a CMP method are provided. The planarization method includes providing a substrate with a first region and a second region having different degrees of hydrophobicity or hydrophilicity and performing a surface treatment to the first region to render the degrees of hydrophobicity or hydrophilicity in proximity to that of the second region. The CMP method includes providing a substrate with a first region and a second region; providing a polishing slurry on the substrate, wherein the polishing slurry and the surface of the first region have a first contact angle, and the polishing slurry and the surface of the first region have a second contact angle; modifying the surface of the first region to make a contact angle difference between the first contact angle and the second contact angle equal to or less than 30 degrees.
    Type: Application
    Filed: June 8, 2018
    Publication date: May 23, 2019
    Inventors: TUNG-KAI CHEN, CHING-HSIANG TSAI, KAO-FENG LIAO, CHIH-CHIEH CHANG, CHUN-HAO KUNG, FANG-I CHIH, HSIN-YING HO, CHIA-JUNG HSU, HUI-CHI HUANG, KEI-WEI CHEN
  • Publication number: 20190157334
    Abstract: The present disclosure is directed to anchor structures and methods for forming anchor structures such that planarization and wafer bonding can be uniform. Anchor structures can include anchor layers formed on a dielectric layer surface and anchor pads formed in the anchor layer and on the dielectric layer surface. The anchor layer material can be selected such that the planarization selectivity of the anchor layer, anchor pads, and the interconnection material can be substantially the same as one another. Anchor pads can provide uniform density of structures that have the same or similar material.
    Type: Application
    Filed: August 6, 2018
    Publication date: May 23, 2019
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chia-Yu WEI, Cheng-Yuan LI, Hsin-Chi CHEN, Kuo-Cheng LEE, Hsun-Ying HUANG, Yen-Liang LIN
  • Publication number: 20190148450
    Abstract: An image sensor device includes a semiconductor substrate, a radiation sensing member, a device layer and a trench isolation. The semiconductor substrate has a front side surface and a back side surface opposite to the front side surface. The radiation sensing member is disposed in a photosensitive region of the semiconductor substrate and extends from the front side surface of the semiconductor substrate. The radiation sensing member includes a semiconductor material with an optical band gap energy smaller than 1.77 eV. The device layer is over the front side surface of the semiconductor substrate and the radiation sensing member. The trench isolation is disposed in an isolation region of the semiconductor substrate and extends from the back side surface of the semiconductor substrate.
    Type: Application
    Filed: November 10, 2017
    Publication date: May 16, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chia-Yu WEI, Yen-Liang LIN, Kuo-Cheng LEE, Hsun-Ying HUANG, Hsin-Chi CHEN
  • Patent number: 9653530
    Abstract: An OLED module equipped with vertical electric connection structure includes a substrate, a plurality of OLED clusters, an anode wire structure and a cathode wire structure. The substrate is extended toward a first direction. The OLED clusters are located on the substrate in the first direction. The anode wire structure includes a bottom layer wire set, an insulation layer, a middle wire layer set and a top layer wire set. The bottom layer wire set is located on the substrate. The insulation layer is located on the bottom layer wire set. The top layer wire set is located on the insulation layer. The cathode wire structure is located on the substrate and extended axially thereof. The middle layer wire set runs through the insulation layer and forms vertical connection between the bottom layer wire set and the top layer wire set.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: May 16, 2017
    Assignee: WiseChip Semiconductor Inc.
    Inventors: Po-Hsin Lin, Shih-Hung Chang, Shang-Chih Lin, Chia-Chi Huang, I-Hsuan Lin, Sheng-Hsu Shih, Chien-Hsun Chen, Yung-Cheng Tsai, Chien-Le Li
  • Patent number: 9508859
    Abstract: A TFT array substrate and a manufacturing method of the same are disclosed by the present disclosure. The TFT array substrate includes a base, a light shielding layer, and a low hydrogen layer. The light shielding layer includes a silicon nitride layer formed on the base, and an amorphous silicon light shielding layer formed on the silicon nitride layer. The low hydrogen layer includes a silicon oxide layer formed on the amorphous silicon light shielding layer of the light shielding layer, and a low hydrogen Poly-Si layer formed on the silicon oxide layer. The layer number of the light shielding layer is equal to that of the low hydrogen layer. The time of manufacturing the light shielding layer matched that of manufacturing the low hydrogen layer, which enhances whole capacity of the TFT array substrate dramatically, and reduces risk of the manufacturing process.
    Type: Grant
    Filed: January 30, 2015
    Date of Patent: November 29, 2016
    Assignee: EverDisplay Optronics (Shanghai) Limited
    Inventors: Chia-chi Huang, Min-ching Hsu
  • Publication number: 20160260793
    Abstract: An OLED module equipped with vertical electric connection structure includes a substrate, a plurality of OLED clusters, an anode wire structure and a cathode wire structure. The substrate is extended toward a first direction. The OLED clusters are located on the substrate in the first direction. The anode wire structure includes a bottom layer wire set, an insulation layer, a middle wire layer set and a top layer wire set. The bottom layer wire set is located on the substrate. The insulation layer is located on the bottom layer wire set. The top layer wire set is located on the insulation layer. The cathode wire structure is located on the substrate and extended axially thereof The middle layer wire set runs through the insulation layer and forms vertical connection between the bottom layer wire set and the top layer wire set.
    Type: Application
    Filed: February 3, 2016
    Publication date: September 8, 2016
    Inventors: Po-Hsin LIN, Shih-Hung CHANG, Shang-Chih LIN, Chia-Chi HUANG, I-Hsuan LIN, Sheng-Hsu SHIH, Chien-Hsun CHEN, Yung-Cheng TSAI, Chien-Le LI
  • Patent number: 9401376
    Abstract: The present application provides a thin film transistor, an active matrix organic light emitting diode assembly and a method for manufacturing the same. The thin film transistor includes: a substrate; a buffer layer on the substrate; a semiconductor layer on the buffer layer, including a source region, a drain region and a channel region; a first gate insulating layer covering the semiconductor layer; a second gate insulating layer foot on the first gate insulating layer, a width of the second gate insulating layer foot being smaller than a width of the first gate insulating layer; and a gate electrode on the second gate insulating layer foot; wherein a part of the first gate insulating layer that is on the semiconductor layer has a flat upper surface. The present application may obtain better implantation profiles of source region and drain region, thereby obtaining better uniformity in TFT performance.
    Type: Grant
    Filed: June 19, 2014
    Date of Patent: July 26, 2016
    Assignee: EverDisplay Optronics (Shanghai) Limited
    Inventors: Chia-Che Hsu, Chia-Chi Huang, Wei-Ting Chen, Min-Ching Hsu
  • Patent number: 9368602
    Abstract: Methods for fabricating an IGZO layer and fabricating TFT are provided in the present invention. The method for fabricating TFT includes the following steps: (1) depositing an IGZO layer and forming a surface oxidizing gas protective layer on the IGZO layer; (2) coating the IGZO layer with a photoresist, and then subjecting the photoresist to an exposing and developing process to form a photoresist pattern; and (3) subjecting the IGZO layer to an etching process, and then removing the photoresist. By forming an oxidizing gas protective layer, the present methods for fabricating an IGZO layer and fabricating TFT can effectively reduce the effect of hydrogen atom on IGZO layer and avoid the change of IGZO layer from semiconductor to conductor, thereby improving the stability of the IGZO layer and thus the TFT, and reducing the negative bias of threshold voltage generated by the long-term continuous use of the device.
    Type: Grant
    Filed: June 27, 2014
    Date of Patent: June 14, 2016
    Assignee: EverDisplay Optronics (Shanghai) Limited
    Inventors: Chia-chi Huang, Min-ching Hsu, Hsueh-ming Tsai, Wen-xia Zuo
  • Publication number: 20160118239
    Abstract: The present disclosure provides A gate insulating layer comprising: a first silicon nitride film having a first thickness and a first content of N—H bonds; a second silicon nitride film having a second thickness and a second content of N—H bonds, disposed on the first silicon nitride film; and a third silicon nitride film having a third thickness and a third content of N—H bonds, disposed on the second silicon nitride film; wherein both the first thickness and the third thickness are less than the second thickness, both the N—H bonds in the first content and the third content are less than that in the second N—H bonds content, and a difference of the N—H bonds between the third content and the first content is no less than 5%. The present disclosure also provides a method for forming the above gate insulating layer.
    Type: Application
    Filed: January 6, 2016
    Publication date: April 28, 2016
    Inventors: Wei-ting CHEN, Chia-chi HUANG, Chunchieh HUANG, Youyuan HU
  • Publication number: 20150311350
    Abstract: A TFT array substrate and a manufacturing method of the same are disclosed by the present disclosure. The TFT array substrate includes a base, a light shielding layer, and a low hydrogen layer. The light shielding layer includes a silicon nitride layer formed on the base, and an amorphous silicon light shielding layer formed on the silicon nitride layer. The low hydrogen layer includes a silicon oxide layer formed on the amorphous silicon light shielding layer of the light shielding layer, and a low hydrogen Poly-Si layer formed on the silicon oxide layer. The layer number of the light shielding layer is equal to that of the low hydrogen layer. The time of manufacturing the light shielding layer matched that of manufacturing the low hydrogen layer, which enhances whole capacity of the TFT array substrate dramatically, and reduces risk of the manufacturing process.
    Type: Application
    Filed: January 30, 2015
    Publication date: October 29, 2015
    Inventors: Chia-chi HUANG, Min-ching HSU
  • Patent number: 9159773
    Abstract: A thin film transistor includes a semiconductor layer including a source region, a drain region, a channel region, first lightly doped drain regions adjacent to the channel region and second lightly doped drain regions adjacent to the first lightly doped drain regions; wherein the second lightly doped drain regions have a doping concentration lower than that of the first lightly doped drain regions. According to the present application, the leakage current in a switching transistor may be further reduced, thereby avoiding instability and even failure in the operation of the assembly caused by overlarge leakage current.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: October 13, 2015
    Assignee: EverDisplay Optronics (Shanghai) Limited
    Inventors: Chia-che Hsu, Chia-chi Huang, Wei-ting Chen, Min-ching Hsu
  • Publication number: 20150129989
    Abstract: The present disclosure provides A gate insulating layer comprising: a first silicon nitride film having a first thickness and a first content of N—H bonds; a second silicon nitride film having a second thickness and a second content of N—H bonds, disposed on the first silicon nitride film; and a third silicon nitride film having a third thickness and a third content of N—H bonds, disposed on the second silicon nitride film; wherein both the first thickness and the third thickness are less than the second thickness, both the N—H bonds in the first content and the third content are less than that in the second N—H bonds content, and a difference of the N—H bonds between the third content and the first content is no less than 5%. The present disclosure also provides a method for forming the above gate insulating layer.
    Type: Application
    Filed: August 19, 2014
    Publication date: May 14, 2015
    Inventors: Wei-ting CHEN, Chia-chi HUANG, Chunchieh HUANG, Youyuan HU
  • Patent number: 8962990
    Abstract: The disclosure provides a multilayer composition containing fluoropolymer and method for fabricating the same, and a solar cell module. The multilayer composition includes: a fluoropolymer layer; a non-fluorinated polymer layer; and an adhesion promoter layer formed between the fluoropolymer layer and the non-fluorinated polymer layer, wherein the adhesion promoter layer includes aromatic diamines or aromatic polyamines.
    Type: Grant
    Filed: April 11, 2012
    Date of Patent: February 24, 2015
    Assignee: Industrial Technology Research Institute
    Inventors: Tien-Shou Shieh, Chia-Chi Huang
  • Publication number: 20150011047
    Abstract: Methods for fabricating an IGZO layer and fabricating TFT are provided in the present invention. The method for fabricating TFT includes the following steps: (1) depositing an IGZO layer and forming a surface oxidizing gas protective layer on the IGZO layer; (2) coating the IGZO layer with a photoresist, and then subjecting the photoresist to an exposing and developing process to form a photoresist pattern; and (3) subjecting the IGZO layer to an etching process, and then removing the photoresist. By forming an oxidizing gas protective layer, the present methods for fabricating an IGZO layer and fabricating TFT can effectively reduce the effect of hydrogen atom on IGZO layer and avoid the change of IGZO layer from semiconductor to conductor, thereby improving the stability of the IGZO layer and thus the TFT, and reducing the negative bias of threshold voltage generated by the long-term continuous use of the device.
    Type: Application
    Filed: June 27, 2014
    Publication date: January 8, 2015
    Inventors: Chia-chi HUANG, Min-ching HSU, Hsueh-ming TSAI, Wen-xia ZUO
  • Publication number: 20140374714
    Abstract: A thin film transistor includes a semiconductor layer including a source region, a drain region, a channel region, first lightly doped drain regions adjacent to the channel region and second lightly doped drain regions adjacent to the first lightly doped drain regions; wherein the second lightly doped drain regions have a doping concentration lower than that of the first lightly doped drain regions. According to the present application, the leakage current in a switching transistor may be further reduced, thereby avoiding instability and even failure in the operation of the assembly caused by overlarge leakage current.
    Type: Application
    Filed: June 6, 2014
    Publication date: December 25, 2014
    Inventors: Chia-che HSU, Chia-chi HUANG, Wei-ting CHEN, Min-ching HSU
  • Publication number: 20140374718
    Abstract: The present application provides a thin film transistor, an active matrix organic light emitting diode assembly and a method for manufacturing the same. The thin film transistor includes: a substrate; a buffer layer on the substrate; a semiconductor layer on the buffer layer, including a source region, a drain region and a channel region; a first gate insulating layer covering the semiconductor layer; a second gate insulating layer foot on the first gate insulating layer, a width of the second gate insulating layer foot being smaller than a width of the first gate insulating layer; and a gate electrode on the second gate insulating layer foot; wherein a part of the first gate insulating layer that is on the semiconductor layer has a flat upper surface. The present application may obtain better implantation profiles of source region and drain region, thereby obtaining better uniformity in TFT performance.
    Type: Application
    Filed: June 19, 2014
    Publication date: December 25, 2014
    Inventors: Chia-Che HSU, Chia-Chi HUANG, Wei-Ting CHEN, Min-Ching HSU
  • Publication number: 20140361276
    Abstract: An active matrix organic light emitting diode assembly includes a substrate and a plurality of pixels on the substrate, each of the pixels at least includes an Organic Light Emitting Diode (OLED), a first Thin Film Transistor (TFT) and a second TFT, wherein: the second TFT is configured to drive the OLED; the first TFT is configured to drive the second TFT, the first TFT includes a buffer layer on the substrate, a semiconductor layer on the buffer layer, a gate insulating layer covering the semiconductor layer and a gate electrode on the gate insulating layer, and the semiconductor layer includes a source region and a drain region of first conductivity type and a bottom doped region of second conductivity type. The leakage current in AMOLED assembly may be suppressed, thereby avoiding instability and even failure of assembly operation caused by overlarge leakage current.
    Type: Application
    Filed: June 6, 2014
    Publication date: December 11, 2014
    Inventors: Chia-che HSU, Chia-chi HUANG, Min-ching HSU
  • Publication number: 20130068303
    Abstract: The disclosure provides a multilayer composition containing fluoropolymer and method for fabricating the same, and a solar cell module. The multilayer composition includes: a fluoropolymer layer; a non-fluorinated polymer layer; and an adhesion promoter layer formed between the fluoropolymer layer and the non-fluorinated polymer layer, wherein the adhesion promoter layer includes aromatic diamines or aromatic polyamines.
    Type: Application
    Filed: April 11, 2012
    Publication date: March 21, 2013
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Tien-Shou SHIEH, Chia-Chi HUANG
  • Patent number: 8367455
    Abstract: A fabricating method of an image sensor includes the steps of: providing a substrate; forming sensing elements on the substrate; forming microlenses on the sensing elements; filling a stuffed material on the microlenses, and air regions are formed in the stuffed material; and forming optical filters on the stuffed material.
    Type: Grant
    Filed: May 30, 2010
    Date of Patent: February 5, 2013
    Assignee: Himax Imaging, Inc.
    Inventors: Yu-Ping Hu, Chih-Wei Hsiung, Fang-Ming Huang, Chia-Chi Huang, Chung-Wei Chang
  • Patent number: 8331477
    Abstract: A progressive parallel interference canceller (PPIC) and a method and a receiver thereof are illustrated. The PPIC reconstructs each subchannel interference reconstruction signal through several iterations and subtracts the corresponding subchannel interference reconstruction signal from each subchannel frequency-domain reception signal to obtain a subchannel frequency-domain signal. Thereby, according to the present disclosure, inter-channel interference can be cancelled without re-performing channel coding or estimating the signal to noise ratio (SNR) or frequency offset.
    Type: Grant
    Filed: September 7, 2009
    Date of Patent: December 11, 2012
    Assignee: Industrial Technology Research Institute
    Inventors: Chao-Wang Huang, Pang-An Ting, Jiun-Yo Lai, Chia-Chi Huang